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OBC-PF-VPX Connector Reference (Final)

CAVU Aerospace UK / PF-VPX OBC / Pinout and Connectors

OBC-PF-VPX – Pinout and Connectors

CAVU Aerospace UK Ltd – 3U SpaceVPX System Controller – SOSA Ed.2 Space Appendix – SLT3-5.1-1 – Rev B

1. SOSA Slot Profile

Authoritative SOSA Ed.2 Space SBC / Coprocessor slot profile – all P0/P1/P2 pin mappings derive from this profile.
FieldValueMeaning
Slot ProfileSLT3-5.1-1SOSA Ed.2 Space SBC / Coprocessor – 3U,
SLT33U slot3U Eurocard form factor (100 أ— 160 mm)
5.1Space SBC familySOSA Space Annex / Space Appendix Single-Board Computer / Coprocessor
-1Dash-1 variant, full copper P1/P2 (no optical / RF apertures)

AMPS Module Profile

MODA3-SBC-( 4E7 )( 4E7 )( 2E7 )( 6E7 )( P2F )( P2F )( P2F )-L2C-( 4E7 )
AMPS FieldMeaning
MODA3-SBCSOSA Module Architecture – 3U Single-Board Computer / Coprocessor class
( 4E7 )Data Plane DP01 – 4 lanes أ— 10GBASE-KR (E7), Fat Pipe
( 4E7 )Data Plane DP02 – 4 lanes أ— 10GBASE-KR (E7), Fat Pipe
( 2E7 )Data Plane DP03 – 2 lanes أ— 10GBASE-KR (E7), Thin Pipe (MSS SGMII1 / 1000BASE-KX capable)
( 6E7 )Control Plane – 6 lanes أ— 10GBASE-KR (E7) Ethernet – CP01 / CP02 / CP03 (SOSA default)
( P2F ) أ—3Expansion Plane – 3 أ— PCIe Gen2 Fat Pipes (أ—4 each) -> EP01 / EP02 / EP03
L2CLevel-2 Compute / Coprocessor class (per SOSA AMPS taxonomy)
( 4E7 )Terminal port reference – 4 أ— 10GBASE-KR capable SerDes reserved

Standards & Mechanical

StandardScopeOBC-PF-VPX
VITA 46.0Connector electrical & mechanicalP0 (8W), P1 (16W), P2 (16W) – MultiGig RT3
VITA 48.2Conduction-cooled mechanicalWedge-lock: Calmark / Birtcher A260-4.80T2
VITA 65.0System-level slot profiles (OpenVPX)SLT3-5.1-1 (Space SBC / Coprocessor, Ethernet CP)
SOSA Ed.2 Space AppendixSpace-qualified restricted subset of VITA 65Aligned – VS1-only power, SM I²C mgmt, NED safety, IPMB maint, Ethernet CP

2. Connector Face Overview

Physical wafer stacking and plane allocation on the module side of the 3U card (SLT3-5.1-1 layout).
OBC-PF-VPX Connector Face 3U SLT3-5.1-1 – SOSA Space SBC – KEY 1 – 315° â†گ Voltage (VS1=12V) P0/J0 Utility Plane W1-2 VS1 W3 SM W4 GA/NED W5 JTAG W6 CLK W7 UTP W8 SPI 8 wafers 72 pins Mgmt+Safety P1/J1 Data + Control (Eth) DP01 FP¹ W1-4 – أ—4 E7² DP02 FP¹ W5-8 – أ—4 E7² DP03 TP W9-10 SGMII³ CP Ethernet – SOSA Default W11-16 – CP01 أ—2 – CP02 أ—2 – CP03 أ—2 (10GBASE-KR) REFCLK + AUX_REFCLK Pairs share wafers with Data / CP signalling 16 wafers 144 pins P2/J2 Expansion Plane EP01 PCIeâپ´ أ—4 – W1-4 PCIe Gen2 Fat Pipe (P2F) EP02 PCIeâپ´ أ—4 – W5-8 PCIe Gen2 Fat Pipe (P2F) EP03 PCIeâپ´ أ—4 W9-12 CLK + SM W13-16 KEY 2 – Slot â†گ Slot ID (per BP) Total: 40 wafers – 360 pins Wedge-lock: Calmark / Birtcher A260-4.80T2
1 FP / TP = Fat Pipe (4 lanes) / Thin Pipe (2 lanes). DP01 and DP02 are E7 Fat Pipes; DP03 is a 2-lane Thin Pipe used for MSS SGMII1 (1000BASE-KX).
2 XCVR / E7 = Multi-gigabit SerDes transceiver. E7 = 10GBASE-KR per SOSA baud-rate class. DP01_LN0_TD+ = Data-Plane group 01, lane 0, Transmit Differential positive.
3 SGMII = Serial Gigabit Media Independent Interface – 1000BASE-KX Ethernet on DP03 thin-pipe lanes, MSS SGMII1 port.
4 PCIe / P2F = PCIe Gen2 أ—4 Fat Pipe – used on the expansion plane EP01 / EP02 / EP03 groups via on-board switch.

3. Color-Coded VPX Pin Tables

Pin data reflects the SOSA Ed.2 Space SBC slot profile SLT3-5.1-1 with .
VS1 (+12V) GND GND-J1/J2 GA / System / Utility Expansion Mgmt / SM / IPMB JTAG / Data Plane (DP) Control Plane – Ethernet (CP) Clocks VBAT NED / Safety 3.3V_AUX Expansion / PCIe (EP) SPI NC No Pad
Hover any cell for the full signal name and SOSA / VITA description. Row ordering: i (top) to a (bottom) per VITA 46 convention. The SoC column on P1 and P2 shows the PolarFire SoC XCVR quad / MAC block assigned to that wafer.

P0/J0 – Utility Plane (72 pins, 8 wafers)

W1-2: VS1 (+12V) – W3: VBAT + mgmt – W4: GA + NED + SYSRESET – W5: JTAG + 3V3_AUX + SM – W6: GA + NED_RETURN – W7: JTAG chain – W8: REF_CLK / AUX_CLK

WRow iRow hRow gRow fRow eRow dRow cRow bRow a
1 GDiscrete1 VS1 VS1 VS1 No Pad NC (VS2) NC (VS2) NC (VS2) NC (VS2)
2 GND VS1 VS1 VS1 No Pad NC (VS2) NC (VS2) NC (VS2) NC (VS2)
3 VBAT NC (VS3) NC (VS3) NC (VS3) No Pad NC (VS3) NC (VS3) NC (VS3) NC (VS3)
4 GND SM2 SM3 GND NED NED SYSRESET* NVMRO GND
5 SYS_CON* GAP* GA4* GND 3V3_AUX GND SM0 SM1 GND
6 GND GA3* GA2* GND NED_RETURN NED_RETURN GA1* GA0* GND
7 TCK GND GND TDO TDI GND GND TMS TRSTB
8 GND REF_CLK_N REF_CLK_P GND GND AUX_CLK_N AUX_CLK_P GND GND
JTAG note (P0-W7): Per VITA 46 and SOSA, the backplane JTAG chain carries only the five digital signals (TCK, TDI, TDO, TMS, TRSTB). No 3.3V VREF / VTARGET is provided on the backplane. FlashPro / SVF programming requires the card to be powered via VS1 (+12V) so the on-board 3.3V_AUX rail supplies VTARGET. The backplane JTAG is for daisy-chained boundary scan only – use the on-module 2أ—5 JTAG header for programming.
NED note (P0-W4 / W6): NED / NED_RETURN is the Nuclear Event Detector single-event discrete per SOSA Ed.2 Rule 13.2.3.1-7 / 13.2.3.1-8 (safety plane). It is a high-reliability dedicated pair – driven by the chassis NED sensor on assertion of a radiation or single-event transient. OBC-PF-VPX latches the event, masks non-essential interrupts, and triggers a controlled reset of the SoC fabric. Must never be repurposed for general I/O.

P1/J1 – Data + (144 pins, 16 wafers)

DP01 Fat Pipe (W1-4, أ—4 E7) – DP02 Fat Pipe (W5-8, أ—4 E7) – DP03 Thin Pipe (W9-10, MSS SGMII1) – CP Ethernet CP01/CP02/CP03 (W11-16) – REFCLK / AUX_REFCLK (shared clock pairs)

WRow iRow hRow gRow fRow eRow dRow cRow bRow aSoC
1 GDiscrete1 GND GND-J1 DP01_LN0_TD- DP01_LN0_TD+ GND GND-J1 DP01_LN0_RD- DP01_LN0_RD+ XCVR1[0]
2 GND DP01_LN1_TD- DP01_LN1_TD+ GND-J1 GND DP01_LN1_RD- DP01_LN1_RD+ GND-J1 GND XCVR1[1]
3 SP_FAIL_A* GND GND-J1 DP01_LN2_TD- DP01_LN2_TD+ GND GND-J1 DP01_LN2_RD- DP01_LN2_RD+ XCVR1[2]
4 GND DP01_LN3_TD- DP01_LN3_TD+ GND-J1 GND DP01_LN3_RD- DP01_LN3_RD+ GND-J1 GND XCVR1[3]
5 SYS_CON* GND GND-J1 DP02_LN0_TD- DP02_LN0_TD+ GND GND-J1 DP02_LN0_RD- DP02_LN0_RD+ XCVR2[0]
6 GND DP02_LN1_TD- DP02_LN1_TD+ GND-J1 GND DP02_LN1_RD- DP02_LN1_RD+ GND-J1 GND XCVR2[1]
7 SYS_CONP* GND GND-J1 DP02_LN2_TD- DP02_LN2_TD+ GND GND-J1 DP02_LN2_RD- DP02_LN2_RD+ XCVR2[2]
8 GND DP02_LN3_TD- DP02_LN3_TD+ GND-J1 GND DP02_LN3_RD- DP02_LN3_RD+ GND-J1 GND XCVR2[3]
9 SM_RESET_A* GND GND-J1 DP03_LN0_TD- DP03_LN0_TD+ GND GND-J1 DP03_LN0_RD- DP03_LN0_RD+ MSS SGMII1
10 GND DP03_LN1_TD- DP03_LN1_TD+ GND-J1 GND DP03_LN1_RD- DP03_LN1_RD+ GND-J1 GND Fabric MAC
11 SM_RESET_B* GND GND-J1 CP01_LN0_TD- CP01_LN0_TD+ GND GND-J1 CP01_LN0_RD- CP01_LN0_RD+ XCVR4[0]
12 GND CP01_LN1_TD- CP01_LN1_TD+ GND-J1 GND CP01_LN1_RD- CP01_LN1_RD+ GND-J1 GND XCVR4[1]
13 SP_FAIL_B* GND GND-J1 CP02_LN0_TD- CP02_LN0_TD+ GND GND-J1 CP02_LN0_RD- CP02_LN0_RD+ XCVR4[2]
14 GND CP02_LN1_TD- CP02_LN1_TD+ GND-J1 GND CP02_LN1_RD- CP02_LN1_RD+ GND-J1 GND XCVR4[3]
15 MaskableReset* GND GND-J1 CP03_LN0_TD- CP03_LN0_TD+ GND GND-J1 CP03_LN0_RD- CP03_LN0_RD+ XCVR3[2]
16 GND CP03_LN1_TD- CP03_LN1_TD+ GND-J1 GND CP03_LN1_RD- CP03_LN1_RD+ GND-J1 GND XCVR3[3]
Control Plane note (P1-W11…W16): The (10GBASE-KR / E7) is the SOSA Ed.2 default for SLT3-5.1-1. CP01 / CP02 / CP03 carry two lanes each – normally operated as 1000BASE-KX under SOSA Space Appendix, with 10GBASE-KR capable backplanes supported. A SpaceWire-based variant is available as a declared legacy option: CP_SpW0..3 would replace CP01-CP03 on the same wafers if a legacy backplane cannot support Ethernet. This version ships with Ethernet enabled by default.
Row E on W1-3 (P1): No Pad – voltage key gap per VITA 46, no physical contact. Ensures the voltage key features clear the mating wafer without shorting.

P2/J2 – Expansion Plane + Redundant Mgmt (144 pins, 16 wafers)

Expansion-plane PCIeâپ´ – EP01 / EP02 / EP03 Fat Pipes (W1-12) – Redundant REF_CLK / AUX_CLK (W13-14) – Redundant IPMB SM0..3_A/B (W15-16) – SPI0 controller (Row i W1-12)

WRow iRow hRow gRow fRow eRow dRow cRow bRow aSoC
1 SPI0_SCK GND GND-J2 EP01_LN0_TD- EP01_LN0_TD+ GND GND-J2 EP01_LN0_RD- EP01_LN0_RD+ PCIe SW DS0[0]
2 GND EP01_LN1_TD- EP01_LN1_TD+ GND-J2 GND EP01_LN1_RD- EP01_LN1_RD+ GND-J2 GND PCIe SW DS0[1]
3 SPI0_SDI GND GND-J2 EP01_LN2_TD- EP01_LN2_TD+ GND GND-J2 EP01_LN2_RD- EP01_LN2_RD+ PCIe SW DS0[2]
4 GND EP01_LN3_TD- EP01_LN3_TD+ GND-J2 GND EP01_LN3_RD- EP01_LN3_RD+ GND-J2 GND PCIe SW DS0[3]
5 SPI0_SDO GND GND-J2 EP02_LN0_TD- EP02_LN0_TD+ GND GND-J2 EP02_LN0_RD- EP02_LN0_RD+ PCIe SW DS1[0]
6 GND EP02_LN1_TD- EP02_LN1_TD+ GND-J2 GND EP02_LN1_RD- EP02_LN1_RD+ GND-J2 GND PCIe SW DS1[1]
7 SPI0_CS0* GND GND-J2 EP02_LN2_TD- EP02_LN2_TD+ GND GND-J2 EP02_LN2_RD- EP02_LN2_RD+ PCIe SW DS1[2]
8 GND EP02_LN3_TD- EP02_LN3_TD+ GND-J2 GND EP02_LN3_RD- EP02_LN3_RD+ GND-J2 GND PCIe SW DS1[3]
9 SPI0_CS1* GND GND-J2 EP03_LN0_TD- EP03_LN0_TD+ GND GND-J2 EP03_LN0_RD- EP03_LN0_RD+ PCIe SW DS2[0]
10 GND EP03_LN1_TD- EP03_LN1_TD+ GND-J2 GND EP03_LN1_RD- EP03_LN1_RD+ GND-J2 GND PCIe SW DS2[1]
11 SPI0_CS2* GND GND-J2 EP03_LN2_TD- EP03_LN2_TD+ GND GND-J2 EP03_LN2_RD- EP03_LN2_RD+ PCIe SW DS2[2]
12 GND EP03_LN3_TD- EP03_LN3_TD+ GND-J2 GND EP03_LN3_RD- EP03_LN3_RD+ GND-J2 GND PCIe SW DS2[3]
13 SYSRESET_A* GND GND-J2 REF_CLK_A_N REF_CLK_A_P GND GND-J2 AUX_CLK_A_N AUX_CLK_A_P Fabric CLK input
14 GND REF_CLK_B_N REF_CLK_B_P GND-J2 GND AUX_CLK_B_N AUX_CLK_B_P GND-J2 GND Fabric CLK input
15 SYSRESET_B* GND GND-J2 SM2_B SM3_B GND GND-J2 SM0_B SM1_B MSS I2C or Fabric
16 GND SM2_A SM3_A GND-J2 GND SM0_A SM1_A GND-J2 GND MSS I2C or Fabric
Abbreviations used in pin names:
1 XCVR – PolarFire SoC multi-gigabit SerDes transceiver quad. DP01_LN0_TD+ = Data Plane group 01, Lane 0, Transmit Differential positive.
2 CP0n_LNn_TD/RD± – (SOSA default). 10GBASE-KR capable SerDes, operated as 1000BASE-KX on space-rated backplanes.
3 DP03 / SGMII – DP03 is a 2-lane Thin Pipe used by MSS SGMII1 for 1000BASE-KX Ethernet.
4 PCIe / EP – Expansion Plane Fat Pipe (P2F = PCIe Gen2 أ—4). EP01_LN0_TD+ = Expansion group 01, Lane 0, TX+.
GA[0..4]*, GAP* – Geographic Address bits with parity, active-low, backplane-determined per slot.
NVMRO – Non-Volatile Memory Read-Only (VITA 46.11) – pulled high to lock NV configuration.
SM[0..3]_A/B – System Management I²C (IPMB) – redundant A/B channels per SOSA Ed.2.
SYSRESET* / SYSRESET_A/B* – System reset, active-low open-drain, redundant per SOSA.
MaskableReset*, SP_FAIL_A/B* – Maskable chassis reset and system-power failure indicators.
GDiscrete1 – Chassis discrete signal per VITA 65 §3.6.
NED / NED_RETURN – Nuclear Event Detector differential discrete – safety-plane signal.

4. Front Panel Connectors

Front-panel I/O is module-specific and not governed by SOSA.
Ethernet / GPIO RS-422 CAN / I²C RS-232 Direct I/O Power out GND

J_FP1 – Gigabit Ethernet (9-pin Micro-D)

SGMII -> 1000BASE-T copper PHY -> magnetic transformer -> front panel

PinSignalDirDescription
1D_PBi1000BASE-T pair D (+)
2C_PBi1000BASE-T pair C (+)
3B_NBi1000BASE-T pair B (−)
4B_PBi1000BASE-T pair B (+)
5A_PBi1000BASE-T pair A (+)
6D_NBi1000BASE-T pair D (−)
7C_NBi1000BASE-T pair C (−)
8A_NBi1000BASE-T pair A (−)
9GNDPWRGround / Shield

J_FP2 – Serial I/O (51-pin Micro-D)

RS-422 أ—2 – CAN أ—2 – RS-232 أ—2 – I²C – GPIO أ—16 (buffered) – DIO أ—8 (direct 3.3V) – Power out (3.3V / 5V @ 500 mA)

PinSignalDirDescription
1RS422_A1OutRS-422 Ch1 TX+ (A)
2RS422_B1OutRS-422 Ch1 TX− (B)
3RS422_Y1InRS-422 Ch1 RX+ (Y)
4RS422_Z1InRS-422 Ch1 RX− (Z)
5RS422_A2OutRS-422 Ch2 TX+ (A)
6RS422_B2OutRS-422 Ch2 TX− (B)
7RS422_Y2InRS-422 Ch2 RX+ (Y)
8RS422_Z2InRS-422 Ch2 RX− (Z)
9GNDPWRGround
10CAN_H1BiCAN bus Ch1 High
11CAN_L1BiCAN bus Ch1 Low
12CAN_H2BiCAN bus Ch2 High
13CAN_L2BiCAN bus Ch2 Low
14GNDPWRGround
15RS232_TX1OutRS-232 Ch1 TXD
16RS232_RX1InRS-232 Ch1 RXD
17RS232_TX2OutRS-232 Ch2 TXD
18RS232_RX2InRS-232 Ch2 RXD
19GNDPWRGround
20I2C_SCLBiI²C clock (3.3V)
21I2C_SDABiI²C data (3.3V)
22GPIO_B1BiBuffered GPIO 1
23GPIO_B2BiBuffered GPIO 2
24GPIO_B3BiBuffered GPIO 3
25GPIO_B4BiBuffered GPIO 4
26GPIO_B5BiBuffered GPIO 5
27GPIO_B6BiBuffered GPIO 6
28GPIO_B7BiBuffered GPIO 7
29GPIO_B8BiBuffered GPIO 8
30GPIO_B9BiBuffered GPIO 9
31GPIO_B10BiBuffered GPIO 10
32GPIO_B11BiBuffered GPIO 11
33GPIO_B12BiBuffered GPIO 12
34GPIO_B13BiBuffered GPIO 13
35GPIO_B14BiBuffered GPIO 14
36GPIO_B15BiBuffered GPIO 15
37GPIO_B16BiBuffered GPIO 16
38GNDPWRGround
39DIO_1BiDirect I/O 1 (3.3V)
40DIO_2BiDirect I/O 2 (3.3V)
41DIO_3BiDirect I/O 3 (3.3V)
42DIO_4BiDirect I/O 4 (3.3V)
43DIO_5BiDirect I/O 5 (3.3V)
44DIO_6BiDirect I/O 6 (3.3V)
45DIO_7BiDirect I/O 7 (3.3V)
46DIO_8BiDirect I/O 8 (3.3V)
47GNDPWRGround
483V3_OUTPWR3.3V output (500 mA max)
495V_OUTPWR5V output (500 mA max)
50NC–Reserved
51GNDPWRGround
RS-422 naming: A = TX+, B = TX−, Y = RX+, Z = RX−
GPIO_B[1..16]: Bank-selectable direction, 3.3/5V factory option, active-buffered
DIO[1..8]: Direct 3.3V LVCMOS I/O from SoC fabric (no buffer)
3V3_OUT / 5V_OUT: 500 mA max each, fused, for external sensor / peripheral power

5. Keying Guide

VITA 46.0 keying – Key 1 is fixed for VS1 voltage, Key 2 identifies slot. Append -Kn suffix to module P/N for slot-specific variant.
3U VPX Keying – OBC-PF-VPX 3U cards have 2 keying positions – 5 possible orientations per VITA 46 Module Side KEY 1 – 315° P0 – 8 wafers P1 – 16 wafers P2 – 16 wafers KEY 2 – Slot Key Pin Orientations Flat side of the keying pin faces the indicated direction 0° 45° 90° 270° 315° Our Key 1 Keying per Backplane Slot Pattern repeats every 5 slots: 270° -> 315° -> 0° -> 45° -> 90° SlotKey 1Key 2 1 (CTL)315°270° 2315°315° 3315°0° 4315°45° 5315°90° Keying Hardware ComponentPart Number Guide Pin (Backplane)1469491-C Guide Module (Card)1469492-C Double-Ended Guide1410956-C

Key 1 – Voltage Key (top, P0/J0 end): Fixed at 315° for all SOSA Ed.2 modules using VS1 = +12V. Prevents insertion of cards with incompatible voltage requirements.

Key 2 – Slot Identification Key (bottom, P1/P2 boundary): Unique per backplane slot. Orientation cycles through 270° -> 315° -> 0° -> 45° -> 90°. The controller slot (Slot 1) uses 270°. Key 2 is backplane-determined – the module guide must match.

Suggested CAVU part number suffix: Since Key 1 is fixed (315°) and Key 2 depends only on the target slot, append -Kn to the module part number where n = slot number (e.g., OBC-PF-VPX-K1 for Slot 1 with Key 2 = 270°). This is the only mechanical variant required.

Keys also serve as chassis ground connections, each capable of carrying up to 20 A. The keying pin orientation is set during assembly and cannot be changed in the field.

6. Abbreviations & Terminology

AbbreviationExpansion & SOSA / VITA Meaning
SpWSpaceWire – ECSS-E-ST-50-12C serial link (Data/Strobe encoding, ≤200 Mbps in SOSA usage). Available as a declared legacy control-plane variant on this module.
XCVRTransceiver – PolarFire SoC multi-gigabit SerDes lane. Four per XCVR quad; pins TD± (TX) and RD± (RX).
SGMIISerial Gigabit Media Independent Interface – 1000BASE-KX backplane Ethernet on MSS SGMII1 (DP03 thin pipe).
PCIePCI Express Gen2 – 5 GT/s per lane, used on the expansion plane EP01 / EP02 / EP03 groups (P2F = Gen2 أ—4 Fat Pipe).
NEDNuclear Event Detector – SOSA Ed.2 safety-plane differential discrete per Rule 13.2.3.1-7 / 13.2.3.1-8. Signals a single-event radiation transient; latches and triggers safed reset.
IPMBIntelligent Platform Management Bus – I²C-based mgmt channel (SM0..3_A/B) per VITA 46.11 / SOSA Ed.2.
UTPUltra-Thin Pipe – 1 SerDes / diff-pair lane (SOSA pipe width).
FPFat Pipe – 4 SerDes lanes ganged (data plane or expansion plane width).
TPThin Pipe – 2 SerDes lanes (DP03 MSS SGMII1 in this profile).
EPExpansion Plane – dedicated inter-module bus (PCIe in this profile). EP01 / EP02 / EP03 = Fat Pipes on P2.
CPControl Plane – SOSA command/telemetry fabric. This profile: Ethernet (CP01/CP02/CP03 = 6 أ— E7 lanes).
DPData Plane – high-bandwidth payload data (DP01/DP02 Fat Pipes + DP03 Thin Pipe on P1).
E710GBASE-KR – 10.3125 GBd backplane Ethernet per IEEE 802.3ap, SOSA baud-rate class E7.
E510GBASE-KX4 – 4 أ— 3.125 GBd backplane Ethernet per IEEE 802.3ap, SOSA baud-rate class E5.
E21000BASE-KX – 1.25 GBd backplane Ethernet per IEEE 802.3ap (Clause 70), SOSA baud-rate class E2.
P2FPCIe Gen2 أ—4 – expansion-plane Fat Pipe port class (5 GT/s أ— 4 lanes).
SWSpaceWire @ 200 Mbps – SOSA control-plane port class for SpW Data/Strobe pairs (declared legacy variant on this module).
CAVU Aerospace UK Ltd – cavuaerospace.uk – SOSA Space SBC SLT3-5.1-1 – – Rev B
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