OBC-Hyper Polar

One add-on set, every current class: 8 solenoid channels at 0.25–0.75 A, 10 auxiliary channels at 7 A continuous / 10 A peak (relays, heaters, devices), 4 TVC actuator channels at 25 A — from a quarter-amp valve to a 25 A actuator on the same two cards.
(Could be increased to any number of outputs)

Multi-hundred-amp class: 100 A on the 36 V bus plus 70 A on the 24 V bus, carried on 3 mm copper busbars and heavy-copper PCB, with sub-watt losses per bar.

Every channel individually protected: an eFuse controller per channel with a ≈ 1 µs short-circuit trip, programmable overload timer, under-voltage lockout and thermal latch with remote sensing of the FET bank.

Controlled turn-on for capacitive loads: a precharge stage starts a 25 A actuator at a resistor-set 60 A, independent of the load capacitance, and the main FET bank closes into a charged output with no inrush — verified against a 1100 A uncontrolled start.

Reverse-polarity immunity without a diode drop: an ideal-diode stage blocks a reversed supply completely (protected side stays at 0 V) and isolates the loads from a collapsing source in ≈ 7 µs, at 4–5 W loss for 100 A.

Compact EMI filtering: ceramic-only, ≤ 2.5 mm high, no magnetics — 24 / 34 / 44 dB at 1 / 3 / 10 kHz; a 60 A channel start moves the bus by only 2 V.

Power and sensing in one package: a dual 16-channel simultaneous-sampling ADC for pressure and analog sensors alongside a 16-channel 1 MSPS health ADC — per-channel current for all 22 outputs, bus voltage and temperatures.

Direct, deterministic control from the OBC-HYPER-POLAR: one FPGA enable per power channel through sacrificial buffers, SPI to the ADCs, I2C to the sensors; a channel can never turn on without a driven command.

Fail-safe by construction: enables default off during FPGA configuration, brown-out or a missing card; the power stage cannot back-power the OBC; buffers are the only thing between the FPGA and the high-voltage board.

Configurable at assembly, not by redesign: start current, protection thresholds, turn-off behaviour, release time, filter fit and grounding policy are fitted values set from a short interface questionnaire — the same boards serve different loads and buses.

Verified before hardware: SPICE with vendor device models for the FET banks, ideal-diode controller and high-side switches, harness and busbar parasitics included; every figure in the deck comes from a netlist that can be re-run.