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OBC-PF-VPX Block Diagram

CAVU Aerospace UK / PF-VPX OBC / Block Diagram

OBC-PF-VPX – Block Diagrams

CAVU Aerospace UK Ltd – 3U SpaceVPX System Controller (SLT3-CTL) – PolarFire- SoC MPFS460T – SOSA Space Aligned

Back To PF-VPX OBC Page Open Pinout and Connectors
1 – OBC-PF-VPX System Block Diagram
CAVU AEROSPACE UK OBC-PF-VPX – 3U SpaceVPX – SOSA Space Aligned – Rev D VPX Backplane Connector – VITA-46 MULTIGIG RT2 – 360 pins P0 – Utility (72 pins) VS1 12V – JTAG – I2C – Debug – USB P1 – Ctrl + Data (144 pins) SpW –4 – XCVR1/2 – SGMII1 – CLK P2 – Data + Expansion (144 pins) XCVR2-4 data – PCIe DS0-3 SpaceWire LVDS –4 ECSS-E-ST-50-12C – LVDS drivers P1 Ctrl Fabric GPIO JTAG Header FlashPro5/6 P0 JTAG JTAG XCVR1-4 16 data lanes SGMII1 USB + Debug RS-232 USB 2.0 ULPI – RS-232 –2 -> P0 W8 P0 Debug MSS UART/USB PolarFire- SoC MPFS460T 461k LE – >4,000 DMIPS – VectorBlox™ AI – Flash-based ZeroFIT RISC-V MSS 4– U54 + E51 monitor CAN –2 – UART – I2C – SPI USB – SGMII0 – SGMII1 PCIe Gen2 –4 (hard block) JTAG FPGA Fabric 461k Logic Elements 784 DSP Blocks SpaceWire IP VectorBlox™ AI GPIO Bank 9 20 XCVR (XCVR0-4, 4 each, up to 12.7 Gbps) XCVR0->PCIe – XCVR1-4->Backplane (16 lanes) PCIe Switch Gen2 – –4 US – DS0/1: –4 – DS2/3: –2 XCVR0 –4 PCIe DS0-3 -> P2 Expansion PCIe Clock Buffer 4– 100 MHz REFCLK outputs REFCLK PMIC 12V -> 5V -> 1.0V / 1.1V / 1.2V / 1.8V / 2.5V / 3.3V LCL protection DDR4 — 9 144 Gbit – 72-bit ECC LPDDR4 – 4 GB –32 – MSS DDR eMMC — 2 512 GB total 2– QSPI NOR 512 Mb – dual boot RTC VBAT backup (P0-W7-e) Monitoring Temp – Current – Voltage GbE PHY SGMII0 -> 1000BASE-T copper SGMII0 Serial I/O Drivers RS-422 –2 – CAN –2 – RS-232 –2 – GPIO MSS + Fabric Front Panel 9-pin Micro-D: GigE copper – 51-pin Micro-D: RS-422 – CAN – RS-232 – GPIO – DIO – I2C Power Budget Input: VS1 +12V (SOSA) On-board 12V -> 5V DC-DC -> PMIC Idle:4.0 W (0.33 A) Nominal:5.5 W (0.46 A) Mem write:7.0 W (0.58 A) Peak:9.5 W (0.79 A) CAVU-OBC-PF-VPX-BD-001 – Rev D – April 2026
2 — VPX Backplane Connector + 4-Slot Backplane Routing
CAVU AEROSPACE UK VITA 46 MultiGig RT2 – SpaceVPX SLT3-5.1-1 – Rev B Connector Face (card side) P0 – Utility – 72 pins – 8 wafers W1VS112V W2VS112V W3VS1VBAT W4MgmtNED W5GA3V3A W6GANED_R W7JTAGchain W8CLKAUX P1 – Data + Control – 144 pins – 16 wafers W1–W4 DP01 XCVR1 FP x4 10G-KR → PAY1 W5–W8 DP02 XCVR2 FP x4 10G-KR → PAY2 W9-10 DP03 SGMII1 KX CP01 XCVR4 [0-1] CP02 XCVR4 [2-3] CP03 XCVR3 [2-3] P2 – Expansion – 144 pins – 16 wafers W1–W4 – EP01 PCIe DS0 x4 → PAY1 W5–W8 – EP02 PCIe DS1 x4 → PAY2 W9–W12 – EP03 PCIe DS2 x4 → PAY3 W13–W16 Util Switch Clk – SM – SPI Voltage key: P0 row e = No Pad (SOSA VS1-only) VS2/VS3: not populated – NC per SOSA Rule 13.2.3.1-2 VBAT: 2.55–3.5 V – <1 mA (Rule 13.2.3.2-1) NED / NED_RETURN replaces legacy ±12V_AUX (Rule 13.2.3.1-7) CP01/02/03 = 10GBASE-KR x2 control per payload 4-Slot SpaceVPX Backplane Routing OBC-PF-VPX SLT3-5.1-1 – Slot 1 PolarFire SoC MPFS460T + fabric PCIe Switch Gen2 From this card: • DP01 x4 (XCVR1 – FP) • DP02 x4 (XCVR2 – FP) • DP03 TP (SGMII1 KX) • CP01 x2 (XCVR4[0-1]) • CP02 x2 (XCVR4[2-3]) • CP03 x2 (XCVR3[2-3]) • EP01 PCIe DS0 x4 • EP02 PCIe DS1 x4 • EP03 PCIe DS2 x4 • Util Switch (clk/SM/SPI) Front Panel 9p µD — GbE 1000BASE-T 51p µD — Serial I/O BACKPLANE PCB PAY Slot 1 DP01 FP x4 – 10GBASE-KR CP01 x2 – EP01 PCIe x4 4E7 + 2E7 + 6E7 (primary payload — 4E7+2E7 + PCIe) P1/P2 PAY Slot 2 DP02 FP x4 – 10GBASE-KR CP02 x2 – EP02 PCIe x4 4E7 + 2E7 + 6E7 (compute / storage payload — symmetric) P1/P2 PAY Slot 3 DP03 TP – 1000BASE-KX CP03 x2 – EP03 PCIe x4 P2F + 2E7 + 6E7 (sensor / aux payload – GbE TP control) P1/P2 PAY Slot 4 – Reserved 12V Utility – Util Switch Mgmt SM – SPI only (no dedicated Data/Expansion pipe) (I/O carrier – future expansion) Pipe Convention (SOSA §13.2) DP01 / DP02 — Data Plane (FP) 4-lane 10GBASE-KR each (4E7) DP03 — Data Plane (TP) 1000BASE-KX – SGMII1 (P2F) CP01/02/03 — Control Plane 10GBASE-KR x2 per payload (2E7) EP01/02/03 — Expansion PCIe Gen2 x4 each (6E7) P0 — Utility Plane VS1, SM, GA, JTAG, CLK, NED Util Switch (P2 W13–16) Redundant clk + mgmt + SPI SOSA Ed.2 Notes • Only VS1 (+12V) populated — VS2/3 NC • VBAT rate-limited to <1 mA • 3V3_AUX always-on for mgmt + RTC • NED/NED_RETURN per Rule 13.2.3.1-7 • UVLO 10V – OVP 14V hot-redundant • MaskableReset* on P1 W15 (fabric) • 4-slot config: 1 SBC + 3 payloads • AUX_CLK_A/B provides hot-redundant PPS Power: SOSA PSU card → VS1 +12V → Backplane P0 W1–W3 → All Slots (hot-redundant pair) UVLO: 10V – OVP: 14V – SBC peak: 9.5 W (0.79 A @ 12V) – VBAT from P0 W3 i-row (≤1 mA) Rev B – SOSA Space SBC SLT3-5.1-1 – April 2026
3 — P0/J0 Utility Plane (8 wafers x 9 rows – 72 pins)
CAVU AEROSPACE UK — OBC-PF-VPX – P0/J0 Utility Plane 72 pins – 8 wafers x 9 rows – VS1 +12V only (SOSA Ed.2 – SLT3-5.1-1) W1 VS1 (+12V) a, c, e, g: +12V b, d, f, h, i: GND Main bus entry (VITA 62 PSU) 9 pins W2 VS1 (+12V) a, c, e, g: +12V b, d, f, h, i: GND Paralleled for high current 9 pins W3 VS1 (+12V) / VBAT a, c, e, g: +12V i: VBAT (~3V) b, d, f, h: GND VS3 NC (SOSA) VBAT ≤1 mA 9 pins W4 Mgmt + NED SM2 – SM3 (IPMB-B) SYSRESET* – NVMRO NED (SOSA) Redundant IPMB-B Safety discretes 9 pins W5 GA + I²C Mgmt GA[4:0] – GAP* SM0 – SM1 (IPMB-A) 3V3_AUX – SYS_CON* Geographic address always-on mgmt rail 9 pins W6 GA + NED Return GA[3:0] NED_RETURN (SOSA) Chassis ground ref for NED signaling (Rule 13.2.3.1-7) 9 pins W7 JTAG TCK – TDO – TDI TMS – TRSTB Daisy-chain through all slots Chassis manager 9 pins W8 Clocks REF_CLK ± AUX_CLK ± 1PPS 100 MHz LVDS from Clock Buffer 9 pins Color Key Power (VS1 +12V / VBAT) Mgmt + NED (IPMB-B – safety) GA + I²C Mgmt (IPMB-A – addr) JTAG (daisy-chained test access) Clocks (REF – AUX – 1PPS) Total: 72 pins – 8 wafers x 9 rows (a–i) – VITA 46 MultiGig RT2 SOSA Ed.2 SLT3-5.1-1 Notes • Only VS1 (+12V) populated — VS2/VS3 NC per Rule 13.2.3.1-2 • VBAT on W3 row i – 2.55–3.5V – rate-limited <1 mA • 3V3_AUX always-on for mgmt controller + RTC • NED / NED_RETURN replaces legacy ±12V_AUX • UVLO 10V – OVP 14V – hot-redundant input protection Rev B – SOSA Space SBC SLT3-5.1-1 – April 2026
4 — P1/J1 Control + Data Plane (16 wafers – 144 pins)
CAVU AEROSPACE UK — OBC-PF-VPX – P1/J1 Data + Control Plane 144 pins – 16 wafers x 9 rows – 10GBASE-KR (DP/CP) + 1000BASE-KX (DP03) DP01 – Fat Pipe (W1–4) XCVR1[0-3] – 10GBASE-KR – 4E7 W1 LN0 → PAY1 (odd) W2 LN1 → PAY1 (even) W3 LN2 → PAY1 W4 LN3 → PAY1 4 lanes x 10 Gb/s Primary data pipe to PAY1 DP02 – Fat Pipe (W5–8) XCVR2[0-3] – 10GBASE-KR – 4E7 W5 LN0 → PAY2 W6 LN1 → PAY2 W7 LN2 → PAY2 W8 LN3 → PAY2 4 lanes x 10 Gb/s Primary data pipe to PAY2 DP03 – TP (W9–10) MSS SGMII1 – 1000BASE-KX 2E7 (thin pipe) W9 LN0 → BP W10 LN1 → BP 1 Gb/s – SGMII1 PAY3 data (TP) CP – Control Plane (W11–16) XCVR4 + XCVR3 – 10GBASE-KR – 6E7 CP01 W11 LN0 W12 LN1 → PAY1 control XCVR4[0-1] CP02 W13 LN0 W14 LN1 → PAY2 control XCVR4[2-3] CP03 W15 LN0 W16 LN1 → PAY3 control XCVR3[2-3] Row I — Utility Expansion Signals (P1) Safety, reset and discrete signals routed on row i of each P1 wafer GDiscrete1 Chassis discrete SP_FAIL_A/B* Redundant PSU fail SYS_CON* System controller SYS_CONP* Primary ctrl flag SM_RESET_A/B* Mgmt reset (redun) MaskableReset* Warm reset (fabric) GND returns + reserves Sprinkled row-i GND pins across W1–16 Per-Slot Pipe Summary PAY1 DP01 Fat Pipe (W1–4): 4x 10GBASE-KR – XCVR1[0-3] CP01 Control (W11–12): 2x 10GBASE-KR – XCVR4[0-1] EP01 Expansion (P2 W1–4): PCIe Gen2 DS0 x4 PAY2 DP02 Fat Pipe (W5–8): 4x 10GBASE-KR – XCVR2[0-3] CP02 Control (W13–14): 2x 10GBASE-KR – XCVR4[2-3] EP02 Expansion (P2 W5–8): PCIe Gen2 DS1 x4 PAY3 DP03 Thin Pipe (W9–10): 1000BASE-KX – MSS SGMII1 CP03 Control (W15–16): 2x 10GBASE-KR – XCVR3[2-3] EP03 Expansion (P2 W9–12): PCIe Gen2 DS2 x4 Rev B – SOSA Space SBC SLT3-5.1-1 – April 2026
5 — P2/J2 Expansion Plane (16 wafers – 144 pins)
CAVU AEROSPACE UK — OBC-PF-VPX – P2/J2 Expansion Plane 144 pins – 16 wafers x 9 rows – PCIe Gen2 x4 per payload + utility switch EP01 (W1–4) PCIe Gen2 DS0 x4 → PAY1 W1 LN0 PCIe x1 W2 LN1 PCIe x1 W3 LN2 PCIe x1 W4 LN3 PCIe x1 4 lanes – 5.0 GT/s From PCIe Switch DS0 x4 EP02 (W5–8) PCIe Gen2 DS1 x4 → PAY2 W5 LN0 PCIe x1 W6 LN1 PCIe x1 W7 LN2 PCIe x1 W8 LN3 PCIe x1 4 lanes – 5.0 GT/s From PCIe Switch DS1 x4 EP03 (W9–12) PCIe Gen2 DS2 x4 → PAY3 W9 LN0 PCIe x1 W10 LN1 PCIe x1 W11 LN2 PCIe x1 W12 LN3 PCIe x1 4 lanes – 5.0 GT/s DS2 – mixed switch + XCVR3[0-1] Utility Switch (W13–16) Redundant clocks + mgmt Redundant Clocks W13 REF_A AUX_A W14 REF_B AUX_B Redundant Mgmt W15 SM0_A SM1_A W16 SM2_B SM3_B Hot-redundant utility fabric SOSA SLT3-5.1-1 Rule 13.2.x Row I — Utility Expansion Signals (P2) SPI management bus + redundant reset routed on row i of P2 wafers SPI0 Bus (SCK / SDI / SDO) Chassis mgmt SPI (P2 W13–16 row i) CS0* – CS1* – CS2* SPI chip-selects (3 PAY slots) SYSRESET_A/B* Redundant system reset AUX_CLK_A/B – REF_CLK_A/B Hot-redundant timing (W13–14) SM0–SM3 A/B (IPMB) Redundant mgmt I²C (W15–16) GND returns + reserves Row-i GND across W1–16 Color Key EP01/02/03 — PCIe Gen2 x4 per payload Utility Switch (W13–16) — redundant clk/mgmt/SPI Row I SPI management bus Row I redundant reset Total: 144 pins – 16 wafers x 9 rows (a–i) – 3x x4 PCIe + utility switch fabric P2 Expansion Notes • DS0/1/2 x4 from onboard PCIe switch (Gen2) • DS2[2-3] routed via XCVR3[0-1] (SoC-direct) • Utility Switch provides hot-redundant fabric • 100 MHz PCIe REFCLK sourced from Clock Buffer • AUX_CLK = 1 PPS distribution (A/B redundant) Rev B – SOSA Space SBC SLT3-5.1-1 – April 2026
6 – OBC-PF-VPX Power Path Block Diagram
CAVU AEROSPACE UK OBC-PF-VPX – Power Path – SOSA Standard (VS1 +12V only) HOT REDUNDANT POWER PATH VPX Backplane P0 Wafers 1-3 VS1 = +12V 27 pins (12V + GND) From SOSA PSU card Hot Redundant +12V Input Protection A UVLO 10V – OVP 14V 1st Stage LCL – Rev. polarity Input Protection B UVLO 10V – OVP 14V 1st Stage LCL – Rev. polarity 12V 12V 12V -> 5V DC-DC A Step-down buck Output: 5.0V 12V -> 5V DC-DC B Step-down buck Output: 5.0V 5V 5V 5V OR + LCL ORing diodes Current limiting Hot-redundant 5V output 5.0V P0 Wafer 5 3.3V_AUX (always-on) 3.3V_AUX Management Only RTC (VBAT backed) P0 Wafer 7-e VBAT (~3V – SOSA) VBAT 3.3V_AUX PMIC 5 BUCK + 4 LDO – LCL Protection 1.0V Core 1.05V PCIe 1.1V MSS DDR 1.2V DDR4 1.8V I/O 2.5V 3.3V Power Distribution Bus PolarFire SoC 1.0V (core logic) 1.8V (I/O banks) 2.5V (XCVR + DDR PHY) MPFS460T DDR4 — 9 1.2V (VDDQ) 144 Gbit – 72-bit ECC ~1.5 W LPDDR4 1.1V (VDD2H) 4 GB – MSS ~0.3 W eMMC — 2 1.8V / 3.3V 512 GB ~0.5 W PCIe Switch 1.05V / 3.3V Gen2 16-port ~2.0 W GbE PHY 1.8V / 2.5V / 3.3V Front panel ~0.5 W I/O + Misc 3.3V / 5V RS-422 – CAN – RS-232 SpW LVDS – USB – GPIO Power Budget Summary Idle 4.0 W Nominal 5.5 W Memory Write 7.0 W Peak (SerDes) 9.5 W Input: VS1 +12V Max: 0.79 A @ 12V Voltage Rails 1.0V – SoC core logic 1.05V – PCIe switch core 1.1V – MSS LPDDR4 1.2V – DDR4 VDDQ 1.8V – I/O, eMMC, GbE PHY 2.5V – XCVR, DDR PHY, GbE PHY 3.3V – GPIO, PHYs, drivers 5.0V – DC-DC output (ORed) 12V – Input from backplane VS1 CAVU-OBC-PF-VPX-BD-006 – Rev D – April 2026
CAVU Aerospace UK Ltd – cavuaerospace.uk – PF-VPX OBC – Architecture Reference – Rev E
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