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CAVU Aerospace UK / PolarStore / Pinout and Connectors

PolarStore — Pinout and Connectors

CAVU Aerospace UK Ltd · PolarStore N-series NVMe storage family · SOSA-aligned 3U VPX · Revision 0.5

Back To PolarStore Product PageGo to Pin TablesView Connector Overview

1. SOSA Slot Profile

Common connector reference for the PolarStore N-series, SOSA-aligned 3U VPX NVMe storage family. Capacity configurations use this page when they share the documented connector allocation and electrical interface revision. Mass, idle power, active power and heat dissipation follow the ordered configuration.

General-purpose storage for compatible PCIe systems. P0 carries power and utilities; P1 retains assigned utility discretes; P2 carries two PCIe Gen2 ×4 channels.

Storage slot profile and role
Profile fieldValueIntegration meaning
Payload designationSLT3-PAY3U payload role; the full slot-profile variant and utility allocation determine compatibility.
SLT33U VPX slot100 × 160 mm board form factor.
PAYPayload moduleStorage function accessed through the backplane PCIe interface.
Data-port allocationP2: two ×4 PCIe Gen2 channelsChannel A at W1–W4; channel B at W5–W8.
P1 allocationData positions reservedRetain the individual utility assignments shown in the pin tables.
Product positioningSOSA alignedSelect a slot with matching power, utility, data routing and mechanical interfaces.

SLT3-PAY identifies the payload role. Use the full slot-profile designation in the module/backplane configuration schedule for slot selection.

AMPS Module Profile

AMPS (Alternate Module Profile Scheme) describes a module using its slot-profile reference and ordered interface fields. The table below lists the storage module interface allocation; it is not a complete AMPS identifier.

3U payload · P2: 2 × PCIe Gen2 ×4 · P0: utility · conduction cooled
AMPS module interface allocation
Module-profile itemPolarStore allocationConnection
Form factor / function3U payload storageSingle-slot, 100 × 160 mm board
PCIe channel AGen2, ×4, 5 GT/s per laneP2 W1–W4; transmit and receive pairs
PCIe channel BGen2, ×4, 5 GT/s per laneP2 W5–W8; transmit and receive pairs
Remaining high-speed data positionsReservedP1 data positions and P2 W9–W12 data positions
Utility servicesPower, clocks, reset, address, management and JTAGIndividual P0/P1/P2 coordinates in section 3
Cooling / depthConduction cooled; 160 mm board depthInstalled pitch and connector datums follow the mechanical drawing
Complete AMPS designationConfiguration-specific module identifierUse the approved module-profile record with the selected slot variant

Standards & Mechanical

Applicable standards and mechanical interfaces
Standard / interfaceScopePolarStore application
VITA 46.0VPX baseline connector and mechanical frameworkP0 / P1 / P2; 8 / 16 / 16 wafers
VITA 46.11VPX system-management frameworkAssigned SM and utility connections as listed; configuration-specific electrical behaviour
VITA 48.2Conduction-cooled VPX mechanical frameworkCard guides, thermal contact and wedge-lock retention
VITA 65OpenVPX slot, module and backplane profilesMatch the complete profile and actual storage connector map
VITA 78SpaceVPX system architectureStorage payload role within the applicable system configuration
SOSAOpen-systems architecture alignmentSOSA-aligned storage module
Board / retention100 × 160 mm; screw-actuated wedge-locks121.92 × 6.35 mm retainer; 6.86 mm maximum relaxed height
Power / thermal interfacePower and heat specified per configurationConduction to chassis cold wall; retention detail in section 5

Storage Interface Summary

Storage interface and connector allocation
FieldPolarStore interfaceIntegration meaning
ArchitectureSOSA-aligned, 3U VPX storageUse the complete storage signal allocation to match the backplane.
CapacitySelected by configuration; two equal logical units8 TB-class example: 7.68 TB nominal per card; 3.84 TB per unit before formatting and RAID metadata.
Data connectionTwo PCIe Gen2 ×4 channelsChannel A: P2 W1–W4. Channel B: P2 W5–W8.
System connectionGeneric compatible PCIe initiator / root complexNo prescribed companion OBC or processor-card family.
P0 / J08 wafers × 9 row positionsSupply, clocks, reset and system utilities.
P1 / J116 wafers × 9 row positionsHigh-speed data positions reserved; assigned utility discretes retained.
P2 / J216 wafers × 9 row positionsPCIe channels, clocks, resets and management; reserved positions as listed.
Power / heatIdle, active and transient values by configurationAt most two storage drives active concurrently per card; conduction to the chassis cold wall.
Mechanical100 × 160 mm board; conduction-cooled 3U VPXScrew-actuated wedge-lock retention; dimensions in section 5.

Optional RAID is configured by the external storage-management system. Two cards provide four logical storage units. This page defines the connector interface; logical-unit identity and access-path mapping follow the delivered storage configuration.

2. Connector Face Overview

P0, P1 and P2 segment overview. The miniature wafer rows use the same i-to-a column order and function colours as the full pin tables.

PolarStore Connector Allocation
P0 / J0Utility
P1 / J1Reserved data / utility
P2 / J2PCIe / utility
40 wafers · 360 logical positions, including key gaps and backplane-only returns.
Allocation schematic; connector mating orientation and keying follow the module/backplane drawing.
PolarStore connector-face schematic: P0 utility, P1 reserved data and assigned utilities, P2 channel A and channel B PCIe x4, followed by reserved data, clocks, resets and management.
Connector-face overview with segment and wafer-group labels. Key 1 is fixed at 315°; Key 2 follows the slot-key schedule in section 5.

P0 / J0 — Utility

VS1 at W1–W2; VBAT at W3; assigned management, address and control signals at W4–W6; JTAG at W7; clock pairs at W8.

P1 / J1 — Assigned Utilities

Data positions are reserved. Row-i discretes retain their individual assignments, including resets, control and fault signals. Reserved positions remain undriven.

P2 / J2 — Storage Data

W1–W4: channel A, four TX pairs and four RX pairs.
W5–W8: channel B, four TX pairs and four RX pairs.
W9–W12: data reserved.
W13–W16: assigned clocks, resets and management.

Direction Convention

IN and OUT are relative to the storage module. Connect storage TX to system RX, and storage RX to system TX.

The full coordinate in each pin cell identifies connector, wafer and row. Section 5 gives the key angles and slot-key schedule; module/backplane drawings define connector datums.

3. Color-Coded VPX Pin Tables

Hover over a signal for its pin description, or click / tap a cell to expand its coordinate and connection note. Keyboard users can focus a cell and press Enter.

VS1 (+12 V)Module groundBackplane returnAddress / system / faultManagement / SMJTAGClocksVBAT3.3 V auxiliaryPCIeReserved / NCNo pad / key gap

Wafer rows run from W1 upward; the position columns run i, h, g, f, e, d, c, b, a. Each signal includes its direction code. On small screens, scroll the tables horizontally.

P0/J0 — Utility Plane (8 wafers, 72 positions)

W1–W2: VS1 · W3: VBAT · W4–W6: management, address and control · W7: JTAG · W8: clocks

P0: position columns i through a; directions relative to the storage module.
WRow iRow hRow gRow fRow eRow dRow cRow bRow a
1
GDiscrete1RES
P0.W1.iDiscrete reserved · RES
Do not drive
VS1PWR
P0.W1.hSupply · PWR
12 V nominal; see electrical interface
VS1PWR
P0.W1.gSupply · PWR
12 V nominal; see electrical interface
VS1PWR
P0.W1.fSupply · PWR
12 V nominal; see electrical interface
No Pad--
P0.W1.eKey gap · --
Key gap; no contact
NC (VS2)NC
P0.W1.dUnused rail · NC
No module connection allocated
NC (VS2)NC
P0.W1.cUnused rail · NC
No module connection allocated
NC (VS2)NC
P0.W1.bUnused rail · NC
No module connection allocated
NC (VS2)NC
P0.W1.aUnused rail · NC
No module connection allocated
2
GNDGND
P0.W2.iReturn · GND
Module signal return
VS1PWR
P0.W2.hSupply · PWR
12 V nominal; see electrical interface
VS1PWR
P0.W2.gSupply · PWR
12 V nominal; see electrical interface
VS1PWR
P0.W2.fSupply · PWR
12 V nominal; see electrical interface
No Pad--
P0.W2.eKey gap · --
Key gap; no contact
NC (VS2)NC
P0.W2.dUnused rail · NC
No module connection allocated
NC (VS2)NC
P0.W2.cUnused rail · NC
No module connection allocated
NC (VS2)NC
P0.W2.bUnused rail · NC
No module connection allocated
NC (VS2)NC
P0.W2.aUnused rail · NC
No module connection allocated
3
VBATPWR
P0.W3.iSupply · PWR
Battery role: electrical interface
NC (VS3)NC
P0.W3.hUnused rail · NC
No module connection allocated
NC (VS3)NC
P0.W3.gUnused rail · NC
No module connection allocated
NC (VS3)NC
P0.W3.fUnused rail · NC
No module connection allocated
No Pad--
P0.W3.eKey gap · --
Key gap; no contact
NC (VS3)NC
P0.W3.dUnused rail · NC
No module connection allocated
NC (VS3)NC
P0.W3.cUnused rail · NC
No module connection allocated
NC (VS3)NC
P0.W3.bUnused rail · NC
No module connection allocated
NC (VS3)NC
P0.W3.aUnused rail · NC
No module connection allocated
4
GNDGND
P0.W4.iReturn · GND
Module signal return
SM2I/O
P0.W4.hMgmt · I/O
Bus pairing: interface schedule
SM3I/O
P0.W4.gMgmt · I/O
Bus pairing: interface schedule
GNDGND
P0.W4.fReturn · GND
Module signal return
NEDRES
P0.W4.eNED reserved · RES
Reserved; do not drive
NEDRES
P0.W4.dNED reserved · RES
Reserved; do not drive
SYSRESET*IN
P0.W4.cControl · IN
Behaviour: electrical interface
NVMROIN
P0.W4.bControl · IN
Behaviour: electrical interface
GNDGND
P0.W4.aReturn · GND
Module signal return
5
SYS_CON*IN
P0.W5.iControl · IN
Behaviour: electrical interface
GAP*IN
P0.W5.hAddress · IN
Address decode: interface schedule
GA4*IN
P0.W5.gAddress · IN
Address decode: interface schedule
GNDGND
P0.W5.fReturn · GND
Module signal return
3V3_AUXPWR
P0.W5.eSupply · PWR
3.3 V nominal; see electrical interface
GNDGND
P0.W5.dReturn · GND
Module signal return
SM0I/O
P0.W5.cMgmt · I/O
Bus pairing: interface schedule
SM1I/O
P0.W5.bMgmt · I/O
Bus pairing: interface schedule
GNDGND
P0.W5.aReturn · GND
Module signal return
6
GNDGND
P0.W6.iReturn · GND
Module signal return
GA3*IN
P0.W6.hAddress · IN
Address decode: interface schedule
GA2*IN
P0.W6.gAddress · IN
Address decode: interface schedule
GNDGND
P0.W6.fReturn · GND
Module signal return
NED_RETURNRES
P0.W6.eNED reserved · RES
Reserved; do not drive
NED_RETURNRES
P0.W6.dNED reserved · RES
Reserved; do not drive
GA1*IN
P0.W6.cAddress · IN
Address decode: interface schedule
GA0*IN
P0.W6.bAddress · IN
Address decode: interface schedule
GNDGND
P0.W6.aReturn · GND
Module signal return
7
TCKIN
P0.W7.iJTAG · IN
Levels/rate: electrical interface
GNDGND
P0.W7.hReturn · GND
Module signal return
GNDGND
P0.W7.gReturn · GND
Module signal return
TDOOUT
P0.W7.fJTAG · OUT
Levels/rate: electrical interface
TDIIN
P0.W7.eJTAG · IN
Levels/rate: electrical interface
GNDGND
P0.W7.dReturn · GND
Module signal return
GNDGND
P0.W7.cReturn · GND
Module signal return
TMSIN
P0.W7.bJTAG · IN
Levels/rate: electrical interface
TRSTBIN
P0.W7.aJTAG · IN
Levels/rate: electrical interface
8
GNDGND
P0.W8.iReturn · GND
Module signal return
REF_CLK_NIN
P0.W8.hClock · IN
Source/receiver: electrical interface
REF_CLK_PIN
P0.W8.gClock · IN
Source/receiver: electrical interface
GNDGND
P0.W8.fReturn · GND
Module signal return
GNDGND
P0.W8.eReturn · GND
Module signal return
AUX_CLK_NIN
P0.W8.dClock · IN
Source/receiver: electrical interface
AUX_CLK_PIN
P0.W8.cClock · IN
Source/receiver: electrical interface
GNDGND
P0.W8.bReturn · GND
Module signal return
GNDGND
P0.W8.aReturn · GND
Module signal return

VS1 is 12 V nominal. The auxiliary connection at P0.W5.e is 3.3 V nominal. VS2 / VS3 positions have no module connection. NED and NED_RETURN are reserved; do not drive them. Supply limits and sequencing follow the delivered electrical interface.

P1/J1 — Reserved Data and Utility Discretes (16 wafers, 144 positions)

Data positions reserved · Assigned row-i control, reset and fault signals retained

P1: position columns i through a; directions relative to the storage module.
WRow iRow hRow gRow fRow eRow dRow cRow bRow a
1
GDiscrete1RES
P1.W1.iDiscrete reserved · RES
Do not drive
GNDGND
P1.W1.hReturn · GND
Module signal return
GND-J1BP
P1.W1.gBP return · BP
Backplane-only position
RESERVEDRES
P1.W1.fReserved · RES
No data service allocated
RESERVEDRES
P1.W1.eReserved · RES
No data service allocated
GNDGND
P1.W1.dReturn · GND
Module signal return
GND-J1BP
P1.W1.cBP return · BP
Backplane-only position
RESERVEDRES
P1.W1.bReserved · RES
No data service allocated
RESERVEDRES
P1.W1.aReserved · RES
No data service allocated
2
GNDGND
P1.W2.iReturn · GND
Module signal return
RESERVEDRES
P1.W2.hReserved · RES
No data service allocated
RESERVEDRES
P1.W2.gReserved · RES
No data service allocated
GND-J1BP
P1.W2.fBP return · BP
Backplane-only position
GNDGND
P1.W2.eReturn · GND
Module signal return
RESERVEDRES
P1.W2.dReserved · RES
No data service allocated
RESERVEDRES
P1.W2.cReserved · RES
No data service allocated
GND-J1BP
P1.W2.bBP return · BP
Backplane-only position
GNDGND
P1.W2.aReturn · GND
Module signal return
3
SP_FAIL_A*OUT
P1.W3.iFault · OUT
Drive/timing: electrical interface
GNDGND
P1.W3.hReturn · GND
Module signal return
GND-J1BP
P1.W3.gBP return · BP
Backplane-only position
RESERVEDRES
P1.W3.fReserved · RES
No data service allocated
RESERVEDRES
P1.W3.eReserved · RES
No data service allocated
GNDGND
P1.W3.dReturn · GND
Module signal return
GND-J1BP
P1.W3.cBP return · BP
Backplane-only position
RESERVEDRES
P1.W3.bReserved · RES
No data service allocated
RESERVEDRES
P1.W3.aReserved · RES
No data service allocated
4
GNDGND
P1.W4.iReturn · GND
Module signal return
RESERVEDRES
P1.W4.hReserved · RES
No data service allocated
RESERVEDRES
P1.W4.gReserved · RES
No data service allocated
GND-J1BP
P1.W4.fBP return · BP
Backplane-only position
GNDGND
P1.W4.eReturn · GND
Module signal return
RESERVEDRES
P1.W4.dReserved · RES
No data service allocated
RESERVEDRES
P1.W4.cReserved · RES
No data service allocated
GND-J1BP
P1.W4.bBP return · BP
Backplane-only position
GNDGND
P1.W4.aReturn · GND
Module signal return
5
SYS_CON*IN
P1.W5.iControl · IN
Behaviour: electrical interface
GNDGND
P1.W5.hReturn · GND
Module signal return
GND-J1BP
P1.W5.gBP return · BP
Backplane-only position
RESERVEDRES
P1.W5.fReserved · RES
No data service allocated
RESERVEDRES
P1.W5.eReserved · RES
No data service allocated
GNDGND
P1.W5.dReturn · GND
Module signal return
GND-J1BP
P1.W5.cBP return · BP
Backplane-only position
RESERVEDRES
P1.W5.bReserved · RES
No data service allocated
RESERVEDRES
P1.W5.aReserved · RES
No data service allocated
6
GNDGND
P1.W6.iReturn · GND
Module signal return
RESERVEDRES
P1.W6.hReserved · RES
No data service allocated
RESERVEDRES
P1.W6.gReserved · RES
No data service allocated
GND-J1BP
P1.W6.fBP return · BP
Backplane-only position
GNDGND
P1.W6.eReturn · GND
Module signal return
RESERVEDRES
P1.W6.dReserved · RES
No data service allocated
RESERVEDRES
P1.W6.cReserved · RES
No data service allocated
GND-J1BP
P1.W6.bBP return · BP
Backplane-only position
GNDGND
P1.W6.aReturn · GND
Module signal return
7
SYS_CONP*IN
P1.W7.iControl · IN
Behaviour: electrical interface
GNDGND
P1.W7.hReturn · GND
Module signal return
GND-J1BP
P1.W7.gBP return · BP
Backplane-only position
RESERVEDRES
P1.W7.fReserved · RES
No data service allocated
RESERVEDRES
P1.W7.eReserved · RES
No data service allocated
GNDGND
P1.W7.dReturn · GND
Module signal return
GND-J1BP
P1.W7.cBP return · BP
Backplane-only position
RESERVEDRES
P1.W7.bReserved · RES
No data service allocated
RESERVEDRES
P1.W7.aReserved · RES
No data service allocated
8
GNDGND
P1.W8.iReturn · GND
Module signal return
RESERVEDRES
P1.W8.hReserved · RES
No data service allocated
RESERVEDRES
P1.W8.gReserved · RES
No data service allocated
GND-J1BP
P1.W8.fBP return · BP
Backplane-only position
GNDGND
P1.W8.eReturn · GND
Module signal return
RESERVEDRES
P1.W8.dReserved · RES
No data service allocated
RESERVEDRES
P1.W8.cReserved · RES
No data service allocated
GND-J1BP
P1.W8.bBP return · BP
Backplane-only position
GNDGND
P1.W8.aReturn · GND
Module signal return
9
SM_RESET_A*IN
P1.W9.iControl · IN
Behaviour: electrical interface
GNDGND
P1.W9.hReturn · GND
Module signal return
GND-J1BP
P1.W9.gBP return · BP
Backplane-only position
RESERVEDRES
P1.W9.fReserved · RES
No data service allocated
RESERVEDRES
P1.W9.eReserved · RES
No data service allocated
GNDGND
P1.W9.dReturn · GND
Module signal return
GND-J1BP
P1.W9.cBP return · BP
Backplane-only position
RESERVEDRES
P1.W9.bReserved · RES
No data service allocated
RESERVEDRES
P1.W9.aReserved · RES
No data service allocated
10
GNDGND
P1.W10.iReturn · GND
Module signal return
RESERVEDRES
P1.W10.hReserved · RES
No data service allocated
RESERVEDRES
P1.W10.gReserved · RES
No data service allocated
GND-J1BP
P1.W10.fBP return · BP
Backplane-only position
GNDGND
P1.W10.eReturn · GND
Module signal return
RESERVEDRES
P1.W10.dReserved · RES
No data service allocated
RESERVEDRES
P1.W10.cReserved · RES
No data service allocated
GND-J1BP
P1.W10.bBP return · BP
Backplane-only position
GNDGND
P1.W10.aReturn · GND
Module signal return
11
SM_RESET_B*IN
P1.W11.iControl · IN
Behaviour: electrical interface
GNDGND
P1.W11.hReturn · GND
Module signal return
GND-J1BP
P1.W11.gBP return · BP
Backplane-only position
RESERVEDRES
P1.W11.fReserved · RES
No data service allocated
RESERVEDRES
P1.W11.eReserved · RES
No data service allocated
GNDGND
P1.W11.dReturn · GND
Module signal return
GND-J1BP
P1.W11.cBP return · BP
Backplane-only position
RESERVEDRES
P1.W11.bReserved · RES
No data service allocated
RESERVEDRES
P1.W11.aReserved · RES
No data service allocated
12
GNDGND
P1.W12.iReturn · GND
Module signal return
RESERVEDRES
P1.W12.hReserved · RES
No data service allocated
RESERVEDRES
P1.W12.gReserved · RES
No data service allocated
GND-J1BP
P1.W12.fBP return · BP
Backplane-only position
GNDGND
P1.W12.eReturn · GND
Module signal return
RESERVEDRES
P1.W12.dReserved · RES
No data service allocated
RESERVEDRES
P1.W12.cReserved · RES
No data service allocated
GND-J1BP
P1.W12.bBP return · BP
Backplane-only position
GNDGND
P1.W12.aReturn · GND
Module signal return
13
SP_FAIL_B*OUT
P1.W13.iFault · OUT
Drive/timing: electrical interface
GNDGND
P1.W13.hReturn · GND
Module signal return
GND-J1BP
P1.W13.gBP return · BP
Backplane-only position
RESERVEDRES
P1.W13.fReserved · RES
No data service allocated
RESERVEDRES
P1.W13.eReserved · RES
No data service allocated
GNDGND
P1.W13.dReturn · GND
Module signal return
GND-J1BP
P1.W13.cBP return · BP
Backplane-only position
RESERVEDRES
P1.W13.bReserved · RES
No data service allocated
RESERVEDRES
P1.W13.aReserved · RES
No data service allocated
14
GNDGND
P1.W14.iReturn · GND
Module signal return
RESERVEDRES
P1.W14.hReserved · RES
No data service allocated
RESERVEDRES
P1.W14.gReserved · RES
No data service allocated
GND-J1BP
P1.W14.fBP return · BP
Backplane-only position
GNDGND
P1.W14.eReturn · GND
Module signal return
RESERVEDRES
P1.W14.dReserved · RES
No data service allocated
RESERVEDRES
P1.W14.cReserved · RES
No data service allocated
GND-J1BP
P1.W14.bBP return · BP
Backplane-only position
GNDGND
P1.W14.aReturn · GND
Module signal return
15
MaskableReset*IN
P1.W15.iControl · IN
Behaviour: electrical interface
GNDGND
P1.W15.hReturn · GND
Module signal return
GND-J1BP
P1.W15.gBP return · BP
Backplane-only position
RESERVEDRES
P1.W15.fReserved · RES
No data service allocated
RESERVEDRES
P1.W15.eReserved · RES
No data service allocated
GNDGND
P1.W15.dReturn · GND
Module signal return
GND-J1BP
P1.W15.cBP return · BP
Backplane-only position
RESERVEDRES
P1.W15.bReserved · RES
No data service allocated
RESERVEDRES
P1.W15.aReserved · RES
No data service allocated
16
GNDGND
P1.W16.iReturn · GND
Module signal return
RESERVEDRES
P1.W16.hReserved · RES
No data service allocated
RESERVEDRES
P1.W16.gReserved · RES
No data service allocated
GND-J1BP
P1.W16.fBP return · BP
Backplane-only position
GNDGND
P1.W16.eReturn · GND
Module signal return
RESERVEDRES
P1.W16.dReserved · RES
No data service allocated
RESERVEDRES
P1.W16.cReserved · RES
No data service allocated
GND-J1BP
P1.W16.bBP return · BP
Backplane-only position
GNDGND
P1.W16.aReturn · GND
Module signal return

Reserved positions are undriven. GND-J1 identifies a backplane-only return position, distinct from a module GND contact. Match each assigned utility to its electrical interface; do not infer function from a neighbouring wafer.

P2/J2 — PCIe Storage and Management (16 wafers, 144 positions)

W1–W4: channel A ×4 · W5–W8: channel B ×4 · W9–W12: data reserved · W13–W16: clock / reset / management

P2: position columns i through a; directions relative to the storage module.
WRow iRow hRow gRow fRow eRow dRow cRow bRow a
1
SPI0_SCKRES
P2.W1.iSPI reserved · RES
Reserved; no command service
GNDGND
P2.W1.hReturn · GND
Module signal return
GND-J2BP
P2.W1.gBP return · BP
Backplane-only position
HOST_A_TX0_NOUT
P2.W1.fPCIe · OUT
Channel A, lane 0
HOST_A_TX0_POUT
P2.W1.ePCIe · OUT
Channel A, lane 0
GNDGND
P2.W1.dReturn · GND
Module signal return
GND-J2BP
P2.W1.cBP return · BP
Backplane-only position
HOST_A_RX0_NIN
P2.W1.bPCIe · IN
Channel A, lane 0
HOST_A_RX0_PIN
P2.W1.aPCIe · IN
Channel A, lane 0
2
GNDGND
P2.W2.iReturn · GND
Module signal return
HOST_A_TX1_NOUT
P2.W2.hPCIe · OUT
Channel A, lane 1
HOST_A_TX1_POUT
P2.W2.gPCIe · OUT
Channel A, lane 1
GND-J2BP
P2.W2.fBP return · BP
Backplane-only position
GNDGND
P2.W2.eReturn · GND
Module signal return
HOST_A_RX1_NIN
P2.W2.dPCIe · IN
Channel A, lane 1
HOST_A_RX1_PIN
P2.W2.cPCIe · IN
Channel A, lane 1
GND-J2BP
P2.W2.bBP return · BP
Backplane-only position
GNDGND
P2.W2.aReturn · GND
Module signal return
3
SPI0_SDIRES
P2.W3.iSPI reserved · RES
Reserved; no command service
GNDGND
P2.W3.hReturn · GND
Module signal return
GND-J2BP
P2.W3.gBP return · BP
Backplane-only position
HOST_A_TX2_NOUT
P2.W3.fPCIe · OUT
Channel A, lane 2
HOST_A_TX2_POUT
P2.W3.ePCIe · OUT
Channel A, lane 2
GNDGND
P2.W3.dReturn · GND
Module signal return
GND-J2BP
P2.W3.cBP return · BP
Backplane-only position
HOST_A_RX2_NIN
P2.W3.bPCIe · IN
Channel A, lane 2
HOST_A_RX2_PIN
P2.W3.aPCIe · IN
Channel A, lane 2
4
GNDGND
P2.W4.iReturn · GND
Module signal return
HOST_A_TX3_NOUT
P2.W4.hPCIe · OUT
Channel A, lane 3
HOST_A_TX3_POUT
P2.W4.gPCIe · OUT
Channel A, lane 3
GND-J2BP
P2.W4.fBP return · BP
Backplane-only position
GNDGND
P2.W4.eReturn · GND
Module signal return
HOST_A_RX3_NIN
P2.W4.dPCIe · IN
Channel A, lane 3
HOST_A_RX3_PIN
P2.W4.cPCIe · IN
Channel A, lane 3
GND-J2BP
P2.W4.bBP return · BP
Backplane-only position
GNDGND
P2.W4.aReturn · GND
Module signal return
5
SPI0_SDORES
P2.W5.iSPI reserved · RES
Reserved; no command service
GNDGND
P2.W5.hReturn · GND
Module signal return
GND-J2BP
P2.W5.gBP return · BP
Backplane-only position
HOST_B_TX0_NOUT
P2.W5.fPCIe · OUT
Channel B, lane 0
HOST_B_TX0_POUT
P2.W5.ePCIe · OUT
Channel B, lane 0
GNDGND
P2.W5.dReturn · GND
Module signal return
GND-J2BP
P2.W5.cBP return · BP
Backplane-only position
HOST_B_RX0_NIN
P2.W5.bPCIe · IN
Channel B, lane 0
HOST_B_RX0_PIN
P2.W5.aPCIe · IN
Channel B, lane 0
6
GNDGND
P2.W6.iReturn · GND
Module signal return
HOST_B_TX1_NOUT
P2.W6.hPCIe · OUT
Channel B, lane 1
HOST_B_TX1_POUT
P2.W6.gPCIe · OUT
Channel B, lane 1
GND-J2BP
P2.W6.fBP return · BP
Backplane-only position
GNDGND
P2.W6.eReturn · GND
Module signal return
HOST_B_RX1_NIN
P2.W6.dPCIe · IN
Channel B, lane 1
HOST_B_RX1_PIN
P2.W6.cPCIe · IN
Channel B, lane 1
GND-J2BP
P2.W6.bBP return · BP
Backplane-only position
GNDGND
P2.W6.aReturn · GND
Module signal return
7
SPI0_CS0*RES
P2.W7.iSPI reserved · RES
Reserved; no command service
GNDGND
P2.W7.hReturn · GND
Module signal return
GND-J2BP
P2.W7.gBP return · BP
Backplane-only position
HOST_B_TX2_NOUT
P2.W7.fPCIe · OUT
Channel B, lane 2
HOST_B_TX2_POUT
P2.W7.ePCIe · OUT
Channel B, lane 2
GNDGND
P2.W7.dReturn · GND
Module signal return
GND-J2BP
P2.W7.cBP return · BP
Backplane-only position
HOST_B_RX2_NIN
P2.W7.bPCIe · IN
Channel B, lane 2
HOST_B_RX2_PIN
P2.W7.aPCIe · IN
Channel B, lane 2
8
GNDGND
P2.W8.iReturn · GND
Module signal return
HOST_B_TX3_NOUT
P2.W8.hPCIe · OUT
Channel B, lane 3
HOST_B_TX3_POUT
P2.W8.gPCIe · OUT
Channel B, lane 3
GND-J2BP
P2.W8.fBP return · BP
Backplane-only position
GNDGND
P2.W8.eReturn · GND
Module signal return
HOST_B_RX3_NIN
P2.W8.dPCIe · IN
Channel B, lane 3
HOST_B_RX3_PIN
P2.W8.cPCIe · IN
Channel B, lane 3
GND-J2BP
P2.W8.bBP return · BP
Backplane-only position
GNDGND
P2.W8.aReturn · GND
Module signal return
9
SPI0_CS1*RES
P2.W9.iSPI reserved · RES
Reserved; no command service
GNDGND
P2.W9.hReturn · GND
Module signal return
GND-J2BP
P2.W9.gBP return · BP
Backplane-only position
RESERVEDRES
P2.W9.fReserved · RES
No data service allocated
RESERVEDRES
P2.W9.eReserved · RES
No data service allocated
GNDGND
P2.W9.dReturn · GND
Module signal return
GND-J2BP
P2.W9.cBP return · BP
Backplane-only position
RESERVEDRES
P2.W9.bReserved · RES
No data service allocated
RESERVEDRES
P2.W9.aReserved · RES
No data service allocated
10
GNDGND
P2.W10.iReturn · GND
Module signal return
RESERVEDRES
P2.W10.hReserved · RES
No data service allocated
RESERVEDRES
P2.W10.gReserved · RES
No data service allocated
GND-J2BP
P2.W10.fBP return · BP
Backplane-only position
GNDGND
P2.W10.eReturn · GND
Module signal return
RESERVEDRES
P2.W10.dReserved · RES
No data service allocated
RESERVEDRES
P2.W10.cReserved · RES
No data service allocated
GND-J2BP
P2.W10.bBP return · BP
Backplane-only position
GNDGND
P2.W10.aReturn · GND
Module signal return
11
SPI0_CS2*RES
P2.W11.iSPI reserved · RES
Reserved; no command service
GNDGND
P2.W11.hReturn · GND
Module signal return
GND-J2BP
P2.W11.gBP return · BP
Backplane-only position
RESERVEDRES
P2.W11.fReserved · RES
No data service allocated
RESERVEDRES
P2.W11.eReserved · RES
No data service allocated
GNDGND
P2.W11.dReturn · GND
Module signal return
GND-J2BP
P2.W11.cBP return · BP
Backplane-only position
RESERVEDRES
P2.W11.bReserved · RES
No data service allocated
RESERVEDRES
P2.W11.aReserved · RES
No data service allocated
12
GNDGND
P2.W12.iReturn · GND
Module signal return
RESERVEDRES
P2.W12.hReserved · RES
No data service allocated
RESERVEDRES
P2.W12.gReserved · RES
No data service allocated
GND-J2BP
P2.W12.fBP return · BP
Backplane-only position
GNDGND
P2.W12.eReturn · GND
Module signal return
RESERVEDRES
P2.W12.dReserved · RES
No data service allocated
RESERVEDRES
P2.W12.cReserved · RES
No data service allocated
GND-J2BP
P2.W12.bBP return · BP
Backplane-only position
GNDGND
P2.W12.aReturn · GND
Module signal return
13
SYSRESET_A*IN
P2.W13.iControl · IN
Behaviour: electrical interface
GNDGND
P2.W13.hReturn · GND
Module signal return
GND-J2BP
P2.W13.gBP return · BP
Backplane-only position
REF_CLK_A_NIN
P2.W13.fClock · IN
Source/receiver: electrical interface
REF_CLK_A_PIN
P2.W13.eClock · IN
Source/receiver: electrical interface
GNDGND
P2.W13.dReturn · GND
Module signal return
GND-J2BP
P2.W13.cBP return · BP
Backplane-only position
AUX_CLK_A_NIN
P2.W13.bClock · IN
Source/receiver: electrical interface
AUX_CLK_A_PIN
P2.W13.aClock · IN
Source/receiver: electrical interface
14
GNDGND
P2.W14.iReturn · GND
Module signal return
REF_CLK_B_NIN
P2.W14.hClock · IN
Source/receiver: electrical interface
REF_CLK_B_PIN
P2.W14.gClock · IN
Source/receiver: electrical interface
GND-J2BP
P2.W14.fBP return · BP
Backplane-only position
GNDGND
P2.W14.eReturn · GND
Module signal return
AUX_CLK_B_NIN
P2.W14.dClock · IN
Source/receiver: electrical interface
AUX_CLK_B_PIN
P2.W14.cClock · IN
Source/receiver: electrical interface
GND-J2BP
P2.W14.bBP return · BP
Backplane-only position
GNDGND
P2.W14.aReturn · GND
Module signal return
15
SYSRESET_B*IN
P2.W15.iControl · IN
Behaviour: electrical interface
GNDGND
P2.W15.hReturn · GND
Module signal return
GND-J2BP
P2.W15.gBP return · BP
Backplane-only position
SM2_BI/O
P2.W15.fMgmt · I/O
Bus pairing: interface schedule
SM3_BI/O
P2.W15.eMgmt · I/O
Bus pairing: interface schedule
GNDGND
P2.W15.dReturn · GND
Module signal return
GND-J2BP
P2.W15.cBP return · BP
Backplane-only position
SM0_BI/O
P2.W15.bMgmt · I/O
Bus pairing: interface schedule
SM1_BI/O
P2.W15.aMgmt · I/O
Bus pairing: interface schedule
16
GNDGND
P2.W16.iReturn · GND
Module signal return
SM2_AI/O
P2.W16.hMgmt · I/O
Bus pairing: interface schedule
SM3_AI/O
P2.W16.gMgmt · I/O
Bus pairing: interface schedule
GND-J2BP
P2.W16.fBP return · BP
Backplane-only position
GNDGND
P2.W16.eReturn · GND
Module signal return
SM0_AI/O
P2.W16.dMgmt · I/O
Bus pairing: interface schedule
SM1_AI/O
P2.W16.cMgmt · I/O
Bus pairing: interface schedule
GND-J2BP
P2.W16.bBP return · BP
Backplane-only position
GNDGND
P2.W16.aReturn · GND
Module signal return

HOST_A_TX and HOST_B_TX are outputs from the storage module; HOST_A_RX and HOST_B_RX are inputs to the storage module. SPI-labelled positions are reserved, with no command service. GND-J2 denotes a backplane-only return.

4. Backplane Lane Routing

Route both ×4 channels to the storage slot. Preserve lane number and differential polarity. The + / − coordinates below are listed in that order.

PCIe lane connections
Channel / laneStorage TX + / −Connect toStorage RX + / −Connect from
A / 0P2.W1.e / P2.W1.fSystem A RX0 + / −P2.W1.a / P2.W1.bSystem A TX0 + / −
A / 1P2.W2.g / P2.W2.hSystem A RX1 + / −P2.W2.c / P2.W2.dSystem A TX1 + / −
A / 2P2.W3.e / P2.W3.fSystem A RX2 + / −P2.W3.a / P2.W3.bSystem A TX2 + / −
A / 3P2.W4.g / P2.W4.hSystem A RX3 + / −P2.W4.c / P2.W4.dSystem A TX3 + / −
B / 0P2.W5.e / P2.W5.fSystem B RX0 + / −P2.W5.a / P2.W5.bSystem B TX0 + / −
B / 1P2.W6.g / P2.W6.hSystem B RX1 + / −P2.W6.c / P2.W6.dSystem B TX1 + / −
B / 2P2.W7.e / P2.W7.fSystem B RX2 + / −P2.W7.a / P2.W7.bSystem B TX2 + / −
B / 3P2.W8.g / P2.W8.hSystem B RX3 + / −P2.W8.c / P2.W8.dSystem B TX3 + / −
  • Select system-side connector coordinates from that system's interface definition.
  • Connect the assigned clock, reset, management, power and return signals in addition to the PCIe lanes.
  • Keep reserved signals undriven. Backplane-only returns and key gaps are not module signal contacts.
  • Match physical connector orientation and keying before insertion.

5. Keying Guide

VITA 46.0 keying — Key 1 is fixed for VS1 voltage, Key 2 identifies slot. Append -Kn suffix to module P/N for slot-specific variant.

3U VPX keying: two key positions, five angle orientations, slot-key schedule and guide hardware.

Key 1 — Voltage Key (top, P0/J0 end): Fixed at 315° for all SOSA Ed.2 modules using VS1 = +12V. Prevents insertion of cards with incompatible voltage requirements.

Key 2 — Slot Identification Key (bottom, P1/P2 boundary): Unique per backplane slot. Orientation cycles through 270° → 315° → 0° → 45° → 90°. The controller slot (Slot 1) uses 270°. Key 2 is backplane-determined — the module guide must match.

Suggested CAVU part number suffix: Since Key 1 is fixed (315°) and Key 2 depends only on the target slot, append -Kn to the module part number where n = slot number (e.g., PolarStore-K1 for Slot 1 with Key 2 = 270°). This is the only mechanical variant required.

Keys also serve as chassis ground connections, each capable of carrying up to 20 A. The keying pin orientation is set during assembly and cannot be changed in the field.

Mechanical Retention and Installation

100 × 160 mm board with conduction cooling and screw-actuated wedge-lock retainers. Module and backplane drawings define connector datums, mating orientation and installed pitch.

Mechanical retention interface
Interface itemDimension / requirement
Board width × depth100 × 160 mm
Retainer body length121.92 mm ±1.3 mm
Retainer width6.35 mm
Retainer relaxed height6.86 mm maximum
Mounting-hole spacing73.66 mm ±0.13 mm
Mounting holesTwo #2-56 tapped holes
Actuation tool3/32 in hex (approximately 2.38 mm)
Actuation torque0.68 N·m (6 lbf·in)
Recommended guide gapRetained assembly thickness + 7.62 mm
Thermal interfaceConduction through module thermal interfaces and card guides to the chassis cold wall

The guide gap is distinct from slot-to-slot pitch. Retainer actuation torque is distinct from mounting-screw torque. Match the module and slot keys; fully release retainers before insertion or extraction. Seat the module before tightening the retainers.

6. Abbreviations and Terminology

Connector terminology
Term / codeMeaning
SLT3 / PAY3U VPX slot / payload role. The full slot-profile variant defines the detailed port arrangement.
AMPSAlternate Module Profile Scheme; a module-profile naming scheme tied to a slot-profile reference and ordered protocol fields.
P0 / P1 / P2Module connector segments; J0 / J1 / J2 identify the corresponding mating segments in this reference.
WWafer number within a connector segment.
P2.W1.aExample coordinate: connector P2, wafer 1, row a.
IN / OUTInput to / output from the storage module.
I/OBidirectional signal.
PWR / GNDPower connection / module ground return.
BP / GND-J1 / GND-J2Backplane-only return position; distinct from a module ground contact.
RES / NCReserved, leave undriven / no module connection.
No Pad / --Key gap; no electrical contact.
PCIe / ×4PCI Express / a four-lane link.
TX / RX; P / NTransmit / receive; positive / negative side of a differential pair.
SMSystem-management signal; exact bus pairing follows the electrical interface.
GA / GAPGeographical address / geographical address parity.
JTAGBoundary-scan test interface; use the supported electrical interface and test procedure.
NEDNuclear Event Detector label; these positions are reserved on this storage allocation.
SOSASensor Open Systems Architecture. Product positioning: SOSA aligned.
TBDecimal terabyte, 10^12 bytes. Capacity class and nominal addressable capacity are distinguished in section 1.
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CAVU Aerospace UK Ltd · PolarStore · Pinout and Connectors · Revision 0.5
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