Edge-64 connector reference for OBC-64: VPX P0/P1/P2 pin maps, SOSA-aligned slot profile details, and mission I/O mappings for integration and verification workflows.

CAVU AEROSPACE UK
Edge-64 Connector Reference

Edge-64 — VPX Connector Reference

Edge-64 · OBC-64 platform pin map and interface reference.

1. SOSA Slot Profile

Field	Value	Meaning
Full Profile	SLT3-5.1-1	SOSA S251A Space SBC / Coprocessor — 3U SpaceVPX payload slot
AMPS Code	F2C	160 mm depth, conduction cooled, 1.0" pitch (Aligned Modular Profile Set)
Board Form Factor	100 × 160 mm	3U Eurocard; both-side component placement
Cooling	Conduction	VITA 48.2; top-side max 12.7 mm, bottom-side max 8.0 mm
Wedge Lock	Calmark/Birtcher A260-4.80T2	Long-edge rails per VITA 48.2
P0 Utility	72 pin MULTIGIG RT2	VS1 +5 V, VS2 +12 V, VA +3.3 V AUX, GA[4:0], IPMB-A/B (dual), JTAG, SYSRESET
P1 Ctrl + Data	144 pin MULTIGIG RT2	3× DP (10GBASE-KR) + 6× CPutp (SpW + 10GBASE-KR hybrid) — SOSA S251A Figure 4
P2 Expansion	144 pin MULTIGIG RT2	3× EP (PCIe Gen3 x4) + Ref Clocks + Utility Switch (TSN) + SPI — SOSA S251A Figure 5

Standard	Scope	Edge-64 Compliance
VITA 46	VPX connector electrical & mechanical	P0 (8 wafer), P1 (16 wafer), P2 (16 wafer) MULTIGIG RT2
VITA 48.2	Conduction-cooled 3U mechanical	Calmark/Birtcher A260-4.80T2 wedge lock, top/bottom height limits enforced
VITA 65	OpenVPX system-level slot profiles	SLT3-5.1-1 Space SBC / Coprocessor profile
VITA 78	SpaceVPX (utility plane, power, GA)	P0 utility plane per VITA 78 §5; VS1/VS2/VA power; GA[4:0]; IPMB
SOSA S251A	Aligned Modular Profile Set (Edition 2)	SLT3-5.1-1 AMPS F2C — CP hybrid: SpW 0–1 + 10GbE CP (CPutp05–06); EP: 3× PCIe Gen3 x4; Utility Switch: TSN 10GbE

2. Connector Face Overview

Module-side view. Backplane connectors P0/P1/P2 on the VPX edge; front-panel Micro-D J4/J5/J6 on the opposite edge. Wedge-lock rails run along both long edges per VITA 48.2. SOSA SLT3-5.1-1 keying position shown at top of P0.

3. P0 / J0 — Utility Plane (72 pins, 8 wafers × 9 rows)

VITA 65.0 Table 3.7-1 / VITA 78 utility plane definition. ~42 of 72 pins assigned; remainder are NC per SOSA Rule 6.1-1 (no user-defined reassignment of profile-defined spares).

VS1 (+5 V)
VS2 (+12 V)
VA (+3.3 V AUX)
GND
GA[4:0]
JTAG
IPMB / Mgmt
Discrete / Reset
Reserved / NC

Pin Group	Signal Name	Count	Dir	Source / Destination	Notes
VS1 (+5 V Main)	+5V_VPX	6	Input	VPX backplane → on-board eFuse	Paralleled for 6 A capacity
VS2 (+12 V Main)	+12V_VPX	4	Input	VPX backplane → power module	Primary high-voltage input; 4 pins × 3.5 A max
VA (+3.3 V AUX)	+3V3_AUX	2	Input	VPX backplane → SAMRH707 IPMC	Always-on auxiliary power
GND	GND	12	—	—	Ground return; interleaved with power pins
GA[4:0]	GA0–GA4	5	Input	Backplane resistor → SAMRH707 GPIO	Geographic slot address
SYSRESET*	SYSRESET_N	1	Input	Backplane → SAMRH707 IPMC	Active-low system reset
NVMRO	NVMRO	1	Input	Backplane → SAMRH707 GPIO	NVM read-only override
HEALTHY	HEALTHY	1	Output	SAMRH707 → backplane	Board health status (active-high)
IPMB-A SCL	IPMB_A_SCL	1	Bidir	Backplane I2C Bus A → SAMRH707 IPMC	IPMB clock, channel A; 3.3 kΩ pull-up on backplane
IPMB-A SDA	IPMB_A_SDA	1	Bidir	Backplane I2C Bus A → SAMRH707 IPMC	IPMB data, channel A
IPMB-B SCL	IPMB_B_SCL	1	Bidir	Backplane I2C Bus B → SAMRH707 IPMC	IPMB clock, channel B (redundant); 3.3 kΩ pull-up on backplane
IPMB-B SDA	IPMB_B_SDA	1	Bidir	Backplane I2C Bus B → SAMRH707 IPMC	IPMB data, channel B (redundant)
JTAG TCK	P0_TCK	1	Input	Backplane JTAG chain → PIC64-HPSC	Boundary-scan chain; optional
JTAG TMS	P0_TMS	1	Input	Backplane JTAG chain → PIC64-HPSC
JTAG TDI	P0_TDI	1	Input	Backplane JTAG chain → PIC64-HPSC
JTAG TDO	P0_TDO	1	Output	PIC64-HPSC → backplane JTAG chain
JTAG TRSTB	P0_TRSTB	1	Input	Backplane → PIC64-HPSC
SM_ALERT*	SM_ALERT_N	1	Output	SAMRH707 → backplane	System management alert
Reserved / NC	—	~30	—	—	Profile-defined spares; left NC per SOSA Rule 6.1-1

Signal names per VITA 65 / VITA 78. Power pins paralleled per signal-integrity rules: VS1 ×6, VS2 ×4, VA ×2, GND ×12 interleaved.
IPMB pull-ups (3.3 kΩ) reside on the backplane per VITA 46. Dual redundant IPMB-A and IPMB-B channels per SOSA and VITA 46.11; both channels active simultaneously — IPMC selects the healthy channel. GA[4:0] is read at power-on by SAMRH707 IPMC to establish the slot address for IPMB enumeration.

4. P1 / J1 — Control + Data Plane (144 pins · SOSA S251A Figure 4 grid)

16 wafer pairs × 7 signal rows (A/B/C/D/E even & odd, F, G). 3× Data Plane (DP01 / DP02 / DP03) + 6× Control Plane UTP (CPutp01–06) per SOSA SLT3-5.1-1 AMPS.

DP — Data Plane (Fat Pipe)
CP — Control Plane UTP
Row G Discretes
GND

Pair	G (Discrete)	F	E even	E odd	D	C even	C odd	B even	B odd	A even	A odd	Pipe	Protocol (ER64)
1	GDiscrete1	GND	GND-J1	DP01-TD0−	DP01-TD0+	GND	GND-J1	DP01-RD0−	DP01-RD0+	GND-J1	GND	FP DP1	10GBASE-KR (Eth Switch Port 0 TX/RX Lane 0)
2	GND	DP01-TD1−	DP01-TD1+	GND-J1	GND	DP01-RD1−	DP01-RD1+	GND-J1	GND	—	—	FP DP1	10GBASE-KR (Eth Switch Port 1 TX/RX Lane 1)
3	SP_FAIL_A*	GND	GND-J1	DP01-TD2−	DP01-TD2+	GND	GND-J1	DP01-RD2−	DP01-RD2+	GND-J1	GND	FP DP1	10GBASE-KR (Eth Switch Port 2 TX/RX Lane 2)
4	GND	DP01-TD3−	DP01-TD3+	GND-J1	GND	DP01-RD3−	DP01-RD3+	GND-J1	GND	—	—	FP DP1	10GBASE-KR (Eth Switch Port 3 TX/RX Lane 3)
5	SYS_CON*	GND	GND-J1	DP02-TD0−	DP02-TD0+	GND	GND-J1	DP02-RD0−	DP02-RD0+	GND-J1	GND	FP DP2	10GBASE-KR (Eth Switch Port 4 TX/RX Lane 0)
6	GND	DP02-TD1−	DP02-TD1+	GND-J1	GND	DP02-RD1−	DP02-RD1+	GND-J1	GND	—	—	FP DP2	10GBASE-KR (Eth Switch Port 5 TX/RX Lane 1)
7	SYS_CONP*	GND	GND-J1	DP02-TD2−	DP02-TD2+	GND	GND-J1	DP02-RD2−	DP02-RD2+	GND-J1	GND	FP DP2	10GBASE-KR (Eth Switch Port 6 TX/RX Lane 2)
8	GND	DP02-TD3−	DP02-TD3+	GND-J1	GND	DP02-RD3−	DP02-RD3+	GND-J1	GND	—	—	FP DP2	10GBASE-KR (Eth Switch Port 7 TX/RX Lane 3)
9	SM_RESET_A*	GND	GND-J1	DP03-TD0−	DP03-TD0+	GND	GND-J1	DP03-RD0−	DP03-RD0+	GND-J1	GND	TP DP3	10GBASE-KR (Eth Switch Port 8 TX/RX Lane 0)
10	GND	DP03-TD1−	DP03-TD1+	GND-J1	GND	DP03-RD1−	DP03-RD1+	GND-J1	GND	—	—	TP DP3	10GBASE-KR (Eth Switch Port 9 TX/RX Lane 1)
11	SM_RESET_B*	GND	GND-J1	CPutp06-TD−	CPutp06-TD+	GND	GND-J1	CPutp06-RD−	CPutp06-RD+	GND-J1	GND	CP	10GBASE-KR — ETH_CP1 (Eth Switch Port 15)
12	GND	CPutp05-TD−	CPutp05-TD+	GND-J1	GND	CPutp05-RD−	CPutp05-RD+	GND-J1	GND	—	—	CP	10GBASE-KR — ETH_CP0 (Eth Switch Port 14)
13	SP_FAIL_B*	GND	GND-J1	CPutp04-TD−	CPutp04-TD+	GND	GND-J1	CPutp04-RD−	CPutp04-RD+	GND-J1	GND	CP	SpW* — SPW1_Sout±/Sin± (SpW Port 1 strobe)
14	GND	CPutp03-TD−	CPutp03-TD+	GND-J1	GND	CPutp03-RD−	CPutp03-RD+	GND-J1	GND	—	—	CP	SpW* — SPW1_Dout±/Din± (SpW Port 1 data)
15	MaskableReset*	GND	GND-J1	CPutp02-TD−	CPutp02-TD+	GND	GND-J1	CPutp02-RD−	CPutp02-RD+	GND-J1	GND	CP	SpW* — SPW0_Sout±/Sin± (SpW Port 0 strobe)
16	GND	CPutp01-TD−	CPutp01-TD+	GND-J1	GND	CPutp01-RD−	CPutp01-RD+	GND-J1	GND	—	—	CP	SpW* — SPW0_Dout±/Din± (SpW Port 0 data)

CP Hybrid (SOSA AMPS Table 7): CPutp01–04 = 2× legacy SpaceWire links (SpW 0 on CPutp01+02, SpW 1 on CPutp03+04 — each SpW link spans 2 CPutp entries to carry Dout/Din + Sout/Sin per ECSS-E-ST-50-12C). CPutp05–06 = 2× 10GBASE-KR Ethernet CP lanes (Switch Ports 14 / 15). SpW is flagged legacy (*) in SOSA S251A and will be deprecated — CPutp05–06 preserve forward Ethernet-only compatibility.

Abbreviations:
¹ DP — Data Plane Fat/Thin Pipe (10GBASE-KR). DP01-TD0+ = Data Plane 01, TX Differential lane 0, positive.
² CPutp — Control Plane Ultra-Thin Pipe (one TX + one RX diff pair per entry).
³ SpW — SpaceWire serial link (ECSS-E-ST-50-12C): Dout/Din = data out/in, Sout/Sin = strobe out/in. LVDS PHY = U10.
⁴ Row G Discretes — Single-ended control: SP_FAIL_A/B*, SYS_CON/SYS_CONP*, SM_RESET_A/B*, MaskableReset*, GDiscrete1 (all driven/received via SAMRH707 or PIC64 GPIO[43:36]).

5. P2 / J2 — Expansion + Utility Switch (144 pins · SOSA S251A Figure 5 grid)

16 wafer pairs × 7 signal rows. 3× Expansion PCIe (EP01 / EP02 / EP03) + Reference Clocks + Utility Switch (TSN 10GbE) + Row G SPI/Ctrl per SOSA SLT3-5.1-1 AMPS.

EP — Expansion PCIe Gen3 x4
REF_CLK / AUX_CLK
Utility Switch (TSN)
Row G SPI / Ctrl
GND

Pair	G (SPI/Ctrl)	F	E even	E odd	D	C even	C odd	B even	B odd	A even	A odd	Pipe	Protocol (ER64)
1	SPI0_SCK	GND	GND-J2	EP01-TD0−	EP01-TD0+	GND	GND-J2	EP01-RD0−	EP01-RD0+	GND-J2	GND	FP EP1	PCIe Gen3 x4 (Port 0 Lane 0)
2	GND	EP01-TD1−	EP01-TD1+	GND-J2	GND	EP01-RD1−	EP01-RD1+	GND-J2	GND	—	—	FP EP1	PCIe Gen3 x4 (Port 0 Lane 1)
3	SPI0_SDI	GND	GND-J2	EP01-TD2−	EP01-TD2+	GND	GND-J2	EP01-RD2−	EP01-RD2+	GND-J2	GND	FP EP1	PCIe Gen3 x4 (Port 0 Lane 2)
4	GND	EP01-TD3−	EP01-TD3+	GND-J2	GND	EP01-RD3−	EP01-RD3+	GND-J2	GND	—	—	FP EP1	PCIe Gen3 x4 (Port 0 Lane 3)
5	SPI0_SDO	GND	GND-J2	EP02-TD0−	EP02-TD0+	GND	GND-J2	EP02-RD0−	EP02-RD0+	GND-J2	GND	FP EP2	PCIe Gen3 x4 (Port 0 Lane 4)
6	GND	EP02-TD1−	EP02-TD1+	GND-J2	GND	EP02-RD1−	EP02-RD1+	GND-J2	GND	—	—	FP EP2	PCIe Gen3 x4 (Port 0 Lane 5)
7	SPI0_CS0*	GND	GND-J2	EP02-TD2−	EP02-TD2+	GND	GND-J2	EP02-RD2−	EP02-RD2+	GND-J2	GND	FP EP2	PCIe Gen3 x4 (Port 0 Lane 6)
8	GND	EP02-TD3−	EP02-TD3+	GND-J2	GND	EP02-RD3−	EP02-RD3+	GND-J2	GND	—	—	FP EP2	PCIe Gen3 x4 (Port 0 Lane 7)
9	SPI0_CS1*	GND	GND-J2	EP03-TD0−	EP03-TD0+	GND	GND-J2	EP03-RD0−	EP03-RD0+	GND-J2	GND	FP EP3	PCIe Gen3 x4 (Port 1 Lane 0) [alt: SpW4]
10	GND	EP03-TD1−	EP03-TD1+	GND-J2	GND	EP03-RD1−	EP03-RD1+	GND-J2	GND	—	—	FP EP3	PCIe Gen3 x4 (Port 1 Lane 1) [alt: SpW4]
11	SPI0_CS2*	GND	GND-J2	EP03-TD2−	EP03-TD2+	GND	GND-J2	EP03-RD2−	EP03-RD2+	GND-J2	GND	FP EP3	PCIe Gen3 x4 (Port 1 Lane 2) [alt: SpW4]
12	GND	EP03-TD3−	EP03-TD3+	GND-J2	GND	EP03-RD3−	EP03-RD3+	GND-J2	GND	—	—	FP EP3	PCIe Gen3 x4 (Port 1 Lane 3) [alt: SpW4]
13	SYSRESET_A*	GND	GND-J2	REF_CLK_A−	REF_CLK_A+	GND	GND-J2	AUX_CLK_A−	AUX_CLK_A+	GND-J2	GND	Ref Clocks	100 MHz PCIe ref / 156.25 MHz Eth ref
14	GND	REF_CLK_B−	REF_CLK_B+	GND-J2	GND	AUX_CLK_B−	AUX_CLK_B+	GND-J2	GND	—	—	Ref Clocks	Redundant PCIe ref / Eth ref
15	SYSRESET_B*	GND	GND-J2	SM2_B	SM3_B	GND	GND-J2	SM0_B	SM1_B	GND-J2	GND	Utility Switch	TSN Endpoint 1 (4× 10GbE) Ch B
16	GND	SM2_A	SM3_A	GND-J2	GND	SM0_A	SM1_A	GND-J2	GND	—	—	Utility Switch	TSN Endpoint 1 (4× 10GbE) Ch A

PCIe mapping: EP01 + EP02 together form one bifurcated PCIe Gen3 x8 port from PIC64-HPSC Port 0 (EP01 = upper x4, EP02 = lower x4). EP03 = PIC64-HPSC PCIe Port 1 (alternative: SpW 4 legacy via SpW* option, selected at order time). Utility Switch on pairs 15–16 carries 4× 10GBASE-KR lanes from the on-board TSN Endpoint 1 per SOSA AMPS E7.

Abbreviations:
¹ EP — Expansion Plane Fat Pipe (PCIe Gen3 x4). EP01-TD0+ = EP 01, TX differential lane 0, positive.
² REF_CLK_A/B — 100 MHz PCIe reference clock (redundant A/B). AUX_CLK_A/B — 156.25 MHz Ethernet reference clock.
³ SM0–SM3 — Utility Switch SerDes pairs (Channel A / B TSN endpoint to backplane switch).
⁴ Row G SPI — Management SPI bus: SPI0_SCK, SPI0_SDI (formerly MISO), SPI0_SDO (formerly MOSI), SPI0_CS0/1/2*. Plus SYSRESET_A/B* redundant resets.

6. J4 — JTAG Debug (9-pin Micro-D, MIL-DTL-83513)

Standard IEEE 1149.1 JTAG chain → PIC64-HPSC. Board provides VCC_TGT (+3.3 V) for probe level-shifting reference.

JTAG signal (TCK/TMS/TDI/TDO/TRSTB)
VCC_TGT (+3.3 V)
GND / SHIELD

Pin	Signal Name	Dir	Source / Destination	Notes
1	TCK	Input	External JTAG probe → PIC64-HPSC	JTAG Test Clock
2	TMS	Input	External JTAG probe → PIC64-HPSC	Test Mode Select
3	TDI	Input	External JTAG probe → PIC64-HPSC	Test Data In
4	TDO	Output	PIC64-HPSC → JTAG probe	Test Data Out
5	TRSTB	Input	External JTAG probe → PIC64-HPSC	Test Reset, active low
6	GND	—	Board GND	Signal ground reference
7	VCC_TGT	Output	Board 3.3 V → JTAG probe	Voltage reference for probe level-shifting
8	GND	—	Board GND
9	SHIELD	—	Chassis / shell	Connector shell; chassis-grounded

7. J5 — SpaceWire Port 7 Emergency Debug (9-pin Micro-D)

Dedicated SpaceWire Port 7 (via LVDS PHY) for direct mission bench-top debug — bypasses backplane. Four LVDS pairs: Dout±, Sout±, Din±, Sin±.

SpaceWire LVDS
GND

Pin	Signal Name	Dir	Source / Destination	Notes
1	SPW7_Dout+	Output	PIC64-HPSC SpW Port 7 → U14 → J5	Data Out (+), LVDS
2	SPW7_Dout−	Output	PIC64-HPSC SpW Port 7 → U14 → J5	Data Out (−), LVDS
3	SPW7_Sout+	Output	PIC64-HPSC SpW Port 7 → U14 → J5	Strobe Out (+), LVDS
4	SPW7_Sout−	Output	PIC64-HPSC SpW Port 7 → U14 → J5	Strobe Out (−), LVDS
5	SPW7_Din+	Input	J5 → U14 → PIC64-HPSC SpW Port 7	Data In (+), LVDS
6	SPW7_Din−	Input	J5 → U14 → PIC64-HPSC SpW Port 7	Data In (−), LVDS
7	SPW7_Sin+	Input	J5 → U14 → PIC64-HPSC SpW Port 7	Strobe In (+), LVDS
8	SPW7_Sin−	Input	J5 → U14 → PIC64-HPSC SpW Port 7	Strobe In (−), LVDS
9	GND	—	Board GND	Signal ground reference

8. J6 — Mission I/O (51-pin Micro-D, MIL-DTL-83513)

Aggregated mission interface: 1× 1000BASE-T copper GbE (GbE PHY Port 0) + 2× UART RS-422 (AppC UART0/1) + 2× I²C (AppC I²C0/1) + 1× SPI (AppC SPI1) + 2× SpaceWire (Ports 5/6, LVDS PHYs) + 8× 3.3 V CMOS GPIO (PIC64-HPSC GPIO[35:28]) + fused 3V3 / 5V auxiliary power.

Ethernet (1000BASE-T)
RS-422 / SpaceWire
I²C
SPI
GPIO (3.3 V CMOS)
Power (3V3 / 5V, fused)
SHIELD / Chassis

Pin	Signal Name	Signal Group	Dir	Source / Destination	Notes
1	ETH0_TX+	GbE Copper (Port 0)	Output	GbE PHY Port 0 → magnetics → J6	1000BASE-T pair A (+)
2	ETH0_TX−	GbE Copper (Port 0)	Output	GbE PHY Port 0 → magnetics → J6	1000BASE-T pair A (−)
3	ETH0_RX+	GbE Copper (Port 0)	Input	J6 → magnetics → GbE PHY Port 0	1000BASE-T pair B (+)
4	ETH0_RX−	GbE Copper (Port 0)	Input	J6 → magnetics → GbE PHY Port 0	1000BASE-T pair B (−)
5	ETH0_CT+	GbE Copper (Port 0)	Bidir	GbE PHY Port 0	1000BASE-T pair C (+)
6	ETH0_CT−	GbE Copper (Port 0)	Bidir	GbE PHY Port 0	1000BASE-T pair C (−)
7	ETH0_MDI_C+	GbE Copper (Port 0)	Bidir	GbE PHY Port 0	1000BASE-T pair D (+)
8	ETH0_MDI_C−	GbE Copper (Port 0)	Bidir	GbE PHY Port 0	1000BASE-T pair D (−)
9	UART0_TXA	UART 0 (RS-422)	Output	AppC UART0 → RS-422 driver → J6	RS-422, 4-wire, TX+
10	UART0_TXB	UART 0 (RS-422)	Output	AppC UART0 → RS-422 driver → J6	RS-422, TX−
11	UART0_RXY	UART 0 (RS-422)	Input	J6 → RS-422 receiver → AppC UART0	RS-422, RX+
12	UART0_RXZ	UART 0 (RS-422)	Input	J6 → RS-422 receiver → AppC UART0	RS-422, RX−
13	UART1_TXA	UART 1 (RS-422)	Output	AppC UART1 → RS-422 driver → J6	RS-422, 4-wire, TX+
14	UART1_TXB	UART 1 (RS-422)	Output	AppC UART1 → RS-422 driver → J6	RS-422, TX−
15	UART1_RXY	UART 1 (RS-422)	Input	J6 → RS-422 receiver → AppC UART1	RS-422, RX+
16	UART1_RXZ	UART 1 (RS-422)	Input	J6 → RS-422 receiver → AppC UART1	RS-422, RX−
17	I2CA_SCL	I2C Bus A	Bidir	AppC I2C0	3.3 V open-drain; 3.3 kΩ pull-up on board
18	I2CA_SDA	I2C Bus A	Bidir	AppC I2C0
19	I2CB_SCL	I2C Bus B	Bidir	AppC I2C1	3.3 V open-drain; 3.3 kΩ pull-up on board
20	I2CB_SDA	I2C Bus B	Bidir	AppC I2C1
21	SPI1_SCK	SPI (AppC SPI1)	Output	AppC SPI1 → J6	3.3 V; SPI clock
22	SPI1_SDO	SPI (AppC SPI1)	Output	AppC SPI1 → J6	SPI data out (SDO, formerly MOSI)
23	SPI1_SDI	SPI (AppC SPI1)	Input	J6 → AppC SPI1	SPI data in (SDI, formerly MISO)
24	SPI1_CS*	SPI (AppC SPI1)	Output	AppC SPI1 → J6	Chip select, active low
25	SPW5_Dout+	SpaceWire Port 5	Output	PIC64-HPSC SpW 5 → U12 → J6	Data Out (+), LVDS
26	SPW5_Dout−	SpaceWire Port 5	Output	PIC64-HPSC SpW 5 → U12 → J6	Data Out (−), LVDS
27	SPW5_Sout+	SpaceWire Port 5	Output	PIC64-HPSC SpW 5 → U12 → J6	Strobe Out (+), LVDS
28	SPW5_Sout−	SpaceWire Port 5	Output	PIC64-HPSC SpW 5 → U12 → J6	Strobe Out (−), LVDS
29	SPW5_Din+	SpaceWire Port 5	Input	J6 → U12 → PIC64-HPSC SpW 5	Data In (+), LVDS
30	SPW5_Din−	SpaceWire Port 5	Input	J6 → U12 → PIC64-HPSC SpW 5	Data In (−), LVDS
31	SPW5_Sin+	SpaceWire Port 5	Input	J6 → U12 → PIC64-HPSC SpW 5	Strobe In (+), LVDS
32	SPW5_Sin−	SpaceWire Port 5	Input	J6 → U12 → PIC64-HPSC SpW 5	Strobe In (−), LVDS
33	SPW6_Dout+	SpaceWire Port 6	Output	PIC64-HPSC SpW 6 → U13 → J6	Data Out (+), LVDS
34	SPW6_Dout−	SpaceWire Port 6	Output	PIC64-HPSC SpW 6 → U13 → J6	Data Out (−), LVDS
35	SPW6_Sout+	SpaceWire Port 6	Output	PIC64-HPSC SpW 6 → U13 → J6	Strobe Out (+), LVDS
36	SPW6_Sout−	SpaceWire Port 6	Output	PIC64-HPSC SpW 6 → U13 → J6	Strobe Out (−), LVDS
37	SPW6_Din+	SpaceWire Port 6	Input	J6 → U13 → PIC64-HPSC SpW 6	Data In (+), LVDS
38	SPW6_Din−	SpaceWire Port 6	Input	J6 → U13 → PIC64-HPSC SpW 6	Data In (−), LVDS
39	SPW6_Sin+	SpaceWire Port 6	Input	J6 → U13 → PIC64-HPSC SpW 6	Strobe In (+), LVDS
40	SPW6_Sin−	SpaceWire Port 6	Input	J6 → U13 → PIC64-HPSC SpW 6	Strobe In (−), LVDS
41	MIO_GPIO[0]	GPIO (mission)	Bidir	PIC64-HPSC GPIO[28]	3.3 V CMOS; 12 mA drive
42	MIO_GPIO[1]	GPIO (mission)	Bidir	PIC64-HPSC GPIO[29]	3.3 V CMOS; 12 mA drive
43	MIO_GPIO[2]	GPIO (mission)	Bidir	PIC64-HPSC GPIO[30]	3.3 V CMOS; 12 mA drive
44	MIO_GPIO[3]	GPIO (mission)	Bidir	PIC64-HPSC GPIO[31]	3.3 V CMOS; 12 mA drive
45	MIO_GPIO[4]	GPIO (mission)	Bidir	PIC64-HPSC GPIO[32]	3.3 V CMOS; 12 mA drive
46	MIO_GPIO[5]	GPIO (mission)	Bidir	PIC64-HPSC GPIO[33]	3.3 V CMOS; 12 mA drive
47	MIO_GPIO[6]	GPIO (mission)	Bidir	PIC64-HPSC GPIO[34]	3.3 V CMOS; 12 mA drive
48	MIO_GPIO[7]	GPIO (mission)	Bidir	PIC64-HPSC GPIO[35]	3.3 V CMOS; 12 mA drive
49	VCC_3V3	Power	Output	Board 3.3 V → J6	500 mA max; polyfuse protected
50	VCC_5V	Power	Output	Board 5 V → J6	500 mA max; fused
51	SHIELD	Chassis	—	Chassis / shell	Shell ground; chassis-connected

GND pins are interleaved with signal pairs per MIL-DTL-83513 best practice (minimum 5 pins dedicated to GND across the 51-pin body). Exact GND positions follow the selected receptacle pinout. 3V3 / 5V outputs are polyfused at 500 mA max each.

9. Signal Legend (Master)

Colour categories used consistently across Sections 3–8. Signal-name conventions follow SOSA S251A Figures 4/5 for backplane connectors and ECSS-E-ST-50-12C for SpaceWire.

Category	Where used	Signal-name pattern
DP — Data Plane (Fat Pipe)	P1 Row A–E (W1–W10)	DP0x-TDn± / DP0x-RDn± (10GBASE-KR)
CP — Control Plane UTP	P1 Row A–E (W11–W16), J5, J6	CPutp0x-TD± / CPutp0x-RD± · SPWn_Dout/Din/Sout/Sin±
EP — Expansion PCIe	P2 Row A–E (W1–W12)	EP0x-TDn± / EP0x-RDn± (PCIe Gen3 x4)
Utility Switch (TSN)	P2 Row A–E (W15–W16)	SM0_A/B … SM3_A/B (10GBASE-KR TSN)
Ref Clock	P2 Row A–E (W13–W14)	REF_CLK_A/B± · AUX_CLK_A/B±
Discretes (Row G, P1)	P1 Row G, P0 mgmt	SP_FAIL_A/B* · SYS_CON/CONP* · SM_RESET_A/B* · IPMB
SPI / Row G Ctrl (P2)	P2 Row G, J6 SPI	SPI0_SCK · SPI0_SDI · SPI0_SDO · SPI0_CSn* · SYSRESET_A/B*
Ethernet / JTAG	J4, J6 (GbE copper)	TCK/TMS/TDI/TDO/TRSTB · ETH0_TX/RX± · ETH0_CT± · ETH0_MDI_C±
GA[4:0] Geographic Addr	P0	GA0–GA4 (5 bits, backplane resistor strap)
IPMB / Management	P0	IPMB_A_SCL/SDA · IPMB_B_SCL/SDA · SM_ALERT* · HEALTHY
VS1 / VA Power	P0, J4 VCC_TGT, J6 3V3/5V	+5V_VPX · +3V3_AUX · VCC_3V3 · VCC_5V
VS2 +12 V Power	P0 (main input to power module)	+12V_VPX
GND / GND-J1 / GND-J2	All connectors	GND (interleaved with every signal pair)
SHIELD / Chassis	J4, J5, J6 shells	SHIELD (connector shell, chassis-grounded)
Reserved / NC	P0 spares	— (left unconnected per SOSA Rule 6.1-1)

Document: CAVU-EDGE-64-CR-001 · Rev A · April 2026 — Connector Reference for OBC-EDGE-64 / Edge-64.
Derived from: CAVU-EDGE-64-ICD-002 Rev 2.0 (Engineering ICD, 2026-04-18) — all pin assignments verified cell-by-cell against SOSA S251A Figures 4/5 and VITA 65/78.
Not for flight release — Rev A is a design-review artefact. CDR sign-off and backplane-integrator confirmation (OI-08) are required before PCB fabrication.

CAVU AEROSPACE UK Ltd · Edge-64 VPX Connector Reference · CAVU-EDGE-64-CR-001 · Rev A