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OBC-64 Block Diagram

Edge-64 block diagrams for OBC-64: system architecture, VPX P0/P1/P2 routing, connector face overview, and power-path mapping for integration and verification workflows.

CAVU AEROSPACE UK Edge-64 Block Diagram

Edge-64 — Block Diagrams

Edge-64 · OBC-64 architecture and interface block-diagram reference.

1 — Edge-64 System Block Diagram
CAVU AEROSPACE UK Edge-64 · OBC-EDGE-64 · 3U SpaceVPX SLT3-5.1-1 · SOSA Space Aligned · Rev B VPX Backplane — VITA 46 MULTIGIG RT2 — 360 pins P0 — Utility (72 pins) +12V · +5V · +3.3V AUX · GA · IPMB · JTAG · Resets P1 — Ctrl + Data (144 pins) 10× 10GBASE-KR · 2× SpW · 2× 10GbE ctrl · Discretes P2 — Expansion (144 pins) 12× PCIe Gen3 · 4× 10GbE util · REF/AUX CLK · SPI Supervisory MCU Rad-hard ARM Cortex-M7 Power seq · DVFS control Housekeeping · temp · watchdog SPI mgmt bus → P2 Row G IPMB (I2C) → P0 chassis IPMB → P0 Boot / I2C GPIO GbE PHY (4-port) SGMII ↔ 1000BASE-T copper → Front Panel J6 GbE → P1 QSGMII LVDS Repeaters × 5 SpW 0–6 buffering / ESD Quad-channel LVDS SpW 0-1 → P1 SpW 0–6 10× 10GBASE-KR FP DP1/2 + TP DP3 12× PCIe Gen3 FP EP1 · EP2 · EP3 +3.3V AUX (always-on) PIC64-HPSC Octa-core 64-bit RISC-V · TID > 50 krad · SEL immune AppC — Application Complex 8× RISC-V cores (RV64GC) DDR4 controllers × 2 (each 80-bit) Ethernet switch (16-port, 10GBASE-KR) PCIe Gen3 (2× x8 or 4× x4) SpaceWire router (7 + SpW7 boot) NVM ctrl × 4 · UART × 5 · I2C × 5 SPI × 4 · GPIO × 64 · HSSTP trace Clocks: 100 MHz ×2 (PCIe/DDR) 156.25 MHz ×2 (Ethernet ref) REFCLK_WDOG SysC — System Controller RISC-V system controller complex Boot management & secure boot BOOT_CFG[5:0] / BOOT_STAT[5:0] Power-mode control · DVFS JTAG client port (IEEE 1149.6) Health telemetry Native interfaces: 16 SerDes lanes (10GBASE-KR) 8 SpaceWire ports (LVDS) 4 NVM · AXI fabric MEMORY DDR4 × 2 · 16 GB x80 DEECE ECC DDR4 QSPI NOR × 2 512 Mb · dual boot A/B NVM SLC Flash — 8 GB Bad-block-free · 1 Gb/s rd NAND — 512 GB ONFI 4.2 · mission data MRAM — 8 MB 40 ns · infinite endurance Power Protection Input switch (7 A) eFuse × 2 · LCL × 4 VTT regulators × 2 (DDR4) UVLO 10V · OVP 14V LDO / eFuse · DC-DC · LCL +12V / +5V from P0 Power rails Front Panel (Conduction-Cooled Bezel) J4 — JTAG 9-pin Micro-D TCK · TMS · TDI · TDO TRSTB · VCC_TGT IEEE 1149.6 J5 — SpW Emergency 9-pin Micro-D SpW Port 7 (RMAP) Dout/Sout/Din/Sin ± Emergency boot · 200 Mb/s J6 — Mission I/O 51-pin Micro-D GbE · RS-422 ×2 · I2C ×2 SPI · SpW 5/6 · GPIO ×8 +3.3V / +5V payload pwr Boot / I2C / GPIO Power Budget Input: +12 V · +5 V · +3.3 V AUX From VPX P0 (SOSA SLT3-5.1-1) Sleep:1 W Reduced:5 W Typical:8 – 15 W Full Operating A:30 W Peak:38 W SOSA Slot Profile: SLT3-5.1-1 (Space SBC / Coprocessor) · AMPS F2C (160 mm, 1.0″, conduction cooled) Radiation: All critical ICs TID > 50 krad · SEL immune · DEECE ECC on DDR4 · ZeroFIT scrubbing on fabric Mechanics: 3U VPX 100 × 160 mm · VITA 48.2 conduction cooled · 24–26 layer PCB · MIL-DTL-83513 Micro-D CAVU-EDGE-64-BD-001 · Rev B · April 2026
2 — VPX Backplane Connector + Payload Routing
CAVU AEROSPACE UK Edge-64 · VPX Backplane Routing · Data plane 100 Gb/s · PCIe Gen3 ×12 Edge-64 SLT3-5.1-1 · Space SBC / Coprocessor PIC64-HPSC · Octa-core 64-bit RISC-V PIC64-HPSC SoC 16× 10GBASE-KR · 2× PCIe Gen3 x8 · 8× SpW DDR4 ×2 · NVM ×4 · integrated Ethernet switch 10 data lanes (10GBASE-KR) → P1 12 PCIe Gen3 lanes → P2 (FP EP1/2/3) 4 SpW + 4 KR ctrl + 8 discretes → P1 4× 10GBASE-KR util + SPI mgmt → P2 +12V · +5V · +3.3V AUX · JTAG · I2C → P0 Front Panel J4:9-pin Micro-D — JTAG debug J5:9-pin Micro-D — SpW7 emergency J6:51-pin Micro-D — Mission I/O GbE · RS-422 ×2 · I2C ×2 · SPI SpW5/6 · GPIO ×8 · 3.3V/5V Wedge-lock rails both sides VITA 48.2 conduction cooled VITA-46 RT2 · P0 + P1 + P2 P0 P1 P2 SpaceVPX BACKPLANE PCB Data Plane — P1 10 lanes · 10GBASE-KR · 100 Gb/s total FP DP1 4 lanes · 40 Gb/s FP DP2 4 lanes · 40 Gb/s TP DP3 2 lanes · 20 Gb/s Control Plane — P1 CPutp01-02: SpW Link 0 · CPutp03-04: SpW Link 1 CPutp05-06: 2× 10GBASE-KR (fwd-compat) ECSS-E-ST-50-12C · up to 200 Mb/s SpW · 10 Gb/s KR Expansion Plane — P2 12 lanes · PCIe Gen3 · up to 96 Gb/s raw FP EP1 x4 (EP1+EP2 = x8) FP EP2 x4 bifurcation FP EP3 x4 (or SpW opt.) Utility Switch + Clocks — P2 4× 10GBASE-KR (rows 15-16, A+B redundant) REF_CLK_A/B 100 MHz · AUX_CLK_A/B 156.25 MHz SPI mgmt (SCK/SDO/SDI/3× CS*) Utility Plane — P0 +12V main (4 pins) · +5V main (6 pins) · +3.3V AUX (2) GA[4:0] · GAP · SYSRESET* · SM_RESET_A/B* HEALTHY · MaskableReset* · IPMB-A/B (dual SCL/SDA) JTAG chain: TCK/TMS/TDI/TDO/TRSTB Backplane Routing Payload Slots 1–4 Each: FP data + CP SpW + EP PCIe lanes FP DP1 → PAY1 (4×KR) · FP DP2 → PAY2 TP DP3 → PAY3 (2×KR) · FP EP1/2 → PAY1/2 FP EP3 → PAY3 · SpW radial to all SpaceVPX System Controller Separate SpaceVPX System Mgr / PSU occupy CTL and PSU slots in chassis Chassis Bulkhead — SpaceWire 2× 9-pin Micro-D from radial SpW via LVDS plus CAVU J5 emergency SpW7 on front panel Signal Legend Data plane · 10GBASE-KR 10 lanes · 100 Gb/s · on-chip switch Control plane · SpW + KR 2 SpW links + 2 KR lanes Expansion plane · PCIe Gen3 12 lanes (x4+x4+x4) · 96 Gb/s raw Utility switch · 10GBASE-KR 4 lanes + REF/AUX clocks + SPI mgmt Utility plane · P0 +12V / +5V / +3.3V AUX · JTAG · IPMB CAVU-EDGE-64-BD-002 · Rev B · April 2026
3 — P0/J0 Utility Plane Detail (72 pins · 8 wafers)
CAVU AEROSPACE UK · Edge-64 · P0 Utility Plane W1 +12 V Main a, c: +12V (2 pins) b, d, e, f, g: GND h, i: spare 9 pins to Input Switch W2 +12V Main (cont.) a, c: +12V (2 pins) paralleled with W1 high current path 9 pins · 4× +12V total W3 +5 V Main a, c, e: +5V (3 pins) b, d, f: GND g, h, i: +5V (cont.) 9 pins · 6× +5V total W4 GA + Resets GA[4:0] · GAP SYS_CON* · SYS_CONP* SYSRESET* · NVMRO to Supervisory MCU W5 I2C Mgmt (IPMB) IPMB_A/B_SCL · IPMB_A/B_SDA AUX_I2C_SCL · SDA HEALTHY · SM_ALERT* to Supervisory MCU I2C W6 JTAG (chain) TCK · TMS · TDI · TDO TRSTB · RTCK IEEE 1149.1 / 1149.6 Daisy-chain all slots W7 AUX Power + VBAT +3.3V AUX (2 pins) +5V AUX (1 pin) VBAT_RTC · WAKE* Always-on → Supervisor W8 Debug · Trace RS-232 TX / RX HSSTP_CLK · HSSTP_D0/D1 Spare · reserved Trace → chassis panel Power — +12V main · +5V main · +3.3V AUX · VBAT System management (VITA 46 / SOSA standard) Debug (routed to chassis debug panel) SOSA SLT3-5.1-1: Uses VS1 (+12V), VS2 (+5V) and 3.3V_AUX per Slot Profile table — all three available on P0. W8 Debug: Routed through backplane to chassis-level panel: RS-232 UART + HSSTP high-speed serial trace. Protection: Input path: input switch (7 A) · UVLO 10V · OVP 14V · reverse-polarity · per-rail LCL. Supervisory: Rad-hard Cortex-M7 reads GA[4:0], runs IPMB, manages power sequence and watchdog. CAVU-EDGE-64-BD-003 · Rev B · April 2026
4 — P1/J1 Control + Data Plane Detail (144 pins · 16 wafer rows)
CAVU AEROSPACE UK · Edge-64 · P1/J1 Ctrl + Data Plane FP DP1 (rows 1–4) 4× 10GBASE-KR Eth Ports 0–3 40 Gb/s aggregate DP01 TD/RD ×4 pairs + GND interleaved → PAY Slot 1 FP DP2 (rows 5–8) 4× 10GBASE-KR Eth Ports 4–7 40 Gb/s aggregate DP02 TD/RD ×4 pairs + GND interleaved → PAY Slot 2 TP DP3 (rows 9–10) 2× 10GBASE-KR Eth Ports 8–9 20 Gb/s aggregate DP03 TD/RD ×2 pairs + GND interleaved → PAY Slot 3 CP (rows 11–16) 2× SpW + 2× KR ctrl CPutp01-02: SpW Link 0 CPutp03-04: SpW Link 1 CPutp05-06: 2× KR (Eth CP) Sin/Sout/Din/Dout ± (ECSS) SpW radial to all payloads Row G Discretes GDiscrete1 SP_FAIL_A/B* SYS_CON* / SYS_CONP* SM_RESET_A/B* MaskableReset* GND on even rows AMPS Profile 4E7 | 4E7 | 2E7 6E7, SpW* Per SOSA S251A Figure 4 16 wafer rows total GND interleaved Topology: All 10 data lanes + 2 SpW + 2 KR ctrl originate from PIC64-HPSC on-chip Ethernet switch and SpW router. SpW naming: ECSS-E-ST-50-12C convention: Sin/Sout/Din/Dout ± per link. CPutp01-02 carry SpW 0, CPutp03-04 carry SpW 1. LVDS buffering: All SpW signals pass through quad-channel LVDS repeaters (×5 total) for ESD protection and signal integrity. SOSA note: Figure 4 row 10 in SOSA S251A shows DP02-TD1+ (typo) — should be DP03-TD1+ per DP03 pipe numbering. Our design uses DP03. CAVU-EDGE-64-BD-004 · Rev B · April 2026
5 — P2/J2 Expansion Plane Detail (144 pins · 16 wafer rows)
CAVU AEROSPACE UK · Edge-64 · P2/J2 Expansion Plane FP EP1 (rows 1–4) PCIe Gen3 x4 Port 0 lanes 0–3 EP01 TD/RD ×4 pairs Combines with EP2 for x8 + GND interleaved → PAY Slot 1 FP EP2 (rows 5–8) PCIe Gen3 x4 Port 0 lanes 4–7 EP02 TD/RD ×4 pairs Bifurcation to x4+x4 + GND interleaved → PAY Slot 2 FP EP3 (rows 9–12) PCIe Gen3 x4 Port 1 lanes 0–3 EP03 TD/RD ×4 pairs Alt: SpW Port 4 (opt.) + GND interleaved → PAY Slot 3 Ref Clocks (rows 13–14) REF_CLK_A/B ± 100 MHz (PCIe ref) AUX_CLK_A/B ± 156.25 MHz (Ethernet ref) SYSRESET_A/B* A/B redundant Util Switch (rows 15–16) 4× 10GBASE-KR SM0–SM3 A/B (TSN) A+B redundant channels Time-sensitive networking endpoint for backplane management plane Row G — SPI Mgmt SPI0_SCK SPI0_SDO / SDI SPI0_CS[0:2]* SYSRESET_A/B* From Supervisory MCU GND on even rows Topology: 12 PCIe Gen3 lanes from PIC64-HPSC (2× x8 bifurcated to 3× x4). 4 utility switch lanes from on-chip Ethernet switch. Clocks: REF_CLK from on-board PCIe clock buffer. AUX_CLK from 156.25 MHz Ethernet reference oscillator. Both A/B redundant. SPI bus: Supervisory MCU drives SPI management bus on Row G. 3 chip-selects for payload-level power/config control. SOSA note: Figure 5 row 4 in SOSA S251A shows EP02-RD3− (typo) — should be EP01-RD3− per EP01 pipe. Our design uses EP01. AMPS: P3F* | P4F | SpW* per SOSA S251A Figure 5. EP3 supports alternative SpW Port 4 configuration. CAVU-EDGE-64-BD-005 · Rev B · April 2026
6 — Connector Face Overview (Card Edge + Front Panel)
CAVU AEROSPACE UK Edge-64 · 3U SpaceVPX Card · 100 × 160 mm · SLT3-5.1-1 · VITA 48.2 conduction cooled Edge-64 — Side View (Card Edge) 3U · 100 × 160 mm PCB · conduction-cooled frame · wedge-lock each side VPX Backplane Edge MULTIGIG RT2 · 3 connectors P0 Utility · 72 pins 8 wafers (W1–W8) Keying: SOSA pos. P1 Ctrl + Data · 144 pins 16 wafers (W1–W16) 10× 10GBASE-KR data 2× SpW ctrl link 2× 10GBASE-KR ctrl P2 Expansion · 144 pins 12 PCIe + 4 KR util REF/AUX CLK · SPI ▲ WEDGE-LOCK RAIL (top) PCB — 24–26 layers · controlled impedance 100 Ω diff (SpW/Ethernet) · 85 Ω diff (PCIe) DDR4 × 2 16 GB total PIC64-HPSC ~45 × 45 mm Top side · heat path Supervisory MCU Boot · IPMB · seq Power Stage DC-DC · LCL SLC / NAND 8 GB · 512 GB LVDS Rpt × 5 SpW 0–6 buffering GbE PHY 4-port copper Clocks (LVDS) 100 MHz ×2 · 156.25 MHz ×2 MRAM · QSPI 8 MB + 512 Mb ×2 Mission I/O routing (to J6) GbE magnetics + RS-422 drivers · SpW LVDS · GPIO buffers · fused +3.3V/+5V Heat conducted through frame to card edge rails (both sides) Operating: −40 °C to +85 °C (board level) ▼ WEDGE-LOCK RAIL (bottom) Front Panel (Bezel) 3× Micro-D · MIL-DTL-83513 J4 9-pin Micro-D JTAG Debug · VCC_TGT 3.3 V J5 9-pin Micro-D SpW Port 7 · RMAP · emergency J6 51-pin Micro-D Mission I/O 1× 1000BASE-T GbE 2× UART RS-422 2× I2C · 1× SPI 2× SpW (port 5/6) Bezel plate · EMI gasket handle top / eject bottom ESD-protected shell bonded Mechanical & Keying Notes SOSA keying:SLT3-5.1-1 profile — P0 and P1 use SOSA-defined keying pins (prevents wrong-slot insertion) Handle / eject:IEEE 1101.2 handle top + ejector bottom (shown schematically — physical part is VITA 48.2) Wedge-lock:Birtcher or Calmark wedge-lock rails both edges — primary thermal path to chassis AMPS code:F2C — 160 mm module length · 1.0″ pitch · conduction cooled CAVU-EDGE-64-BD-006 · Rev B · April 2026
7 — Edge-64 Power Path Block Diagram
CAVU AEROSPACE UK Edge-64 · Power Path · SOSA SLT3-5.1-1 · VS1 +12V + VS2 +5V + +3.3V AUX VPX Backplane P0 W1-W2: +12 V Main (VS1 · 4 pins · up to 7 A) W3: +5 V Main (VS2 · 6 pins) W7: +3.3V AUX (always-on · VBAT_RTC) Input Protection Switch 7 A · UVLO 10V · OVP 14V reverse-polarity · eFuse +12V eFuse × 2 Hot-swap + current limit programmable slew & OCP +12V 12V → 5V DC-DC Rad-tolerant buck 5.0V intermediate rail 12V bus 5.0 V +5V input filter EMI + eFuse +5V 3.3V AUX path Always-on · Supervisor pwr VBAT_RTC backup +3.3V AUX Supervisor Rad-hard Cortex-M7 · always-on Drives ENABLE to every DC-DC Reads PGOOD flags Power-good Supervisor Multi-rail window comparator Generates HEALTHY + RESET 5.0 V Intermediate Power Distribution Bus 0.8V VDD core Multiphase buck Highest current rail PIC64-HPSC core — LCL protected 0.9V AVD (LDO) Low-noise LDO AVD_ENET (SerDes) AVD_PCIE_HSSTP — LCL protected 1.2V VDDIO_DDR Buck converter DDR4 VDDQ rail DDR4 modules ×2 — LCL protected 1.8V VDDHV Buck converter VDDHV + AVDHV_ENET AVDHV_PCIE_HSSTP — LCL protected 3.3V Housekeeping Buck converter GbE PHY, LVDS rpt NVM, I/O, drivers — LCL protected VTT Regs × 2 Source/sink tracker one per DDR4 module DDR4 VTT · 0.6 V tracks 1.2V/2 Other 2.5V (clocks) 1.5V (HSSTP) VPP_NVM 3.3V/5V on J6 LCL × 4 — Per-Rail Latching Current Limiters (re-triggerable) Over-current trip, SET/RESET by Supervisor, telemetry to IPMB PIC64-HPSC 0.8V core · 1.8V I/O 0.9V AVD · VDDHV main processor SerDes + PCIe 0.9V analog 1.8V HV analog 16 KR + 16 PCIe lanes DDR4 × 2 (16 GB) 1.2V VDDQ 0.6V VTT (×2) DEECE ECC NVM Suite 1.8V / 3.3V QSPI · SLC · NAND · MRAM 520.5 GB total I/O + PHYs 3.3V digital GbE PHY · LVDS rpt RS-422 · UART · GPIO Clocks + Misc 2.5V / 3.3V LVDS oscillators ×4 PCIe clock buffer Payload J6 +3.3V fused +5V fused 500 mA each Power Sequencing & Supervision Supervisor (Cortex-M7): • Asserts ENABLE per DC-DC in PIC64-HPSC-specified order • Monitors PGOOD flags & rail currents via I2C • Resets LCLs after transients (latching) • Drives HEALTHY pin on P0 when all rails within tolerance Power Budget Summary Sleep 1 W Supervisor + MRAM Reduced 5 W PIC64 low-freq Typical 8 – 15 W mission mode Full Op A 30 W all cores/links Voltage Rails 0.8V — PIC64-HPSC core (multiphase) 0.9V — AVD ENET / PCIE HSSTP (LDO) 1.2V — DDR4 VDDQ 1.8V — VDDHV + AVDHV ENET / PCIE 3.3V — housekeeping, PHYs, LVDS 0.6V — DDR4 VTT (×2) 5.0V — intermediate bus + payload +3.3V AUX — always-on (W7) Control — Supervisor ENABLE / PGOOD Protection — LCL (per rail) Input switch (UVLO/OVP) CAVU-EDGE-64-BD-007 · Rev B · April 2026
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CAVU-EDGE-64-BD-001 · Rev B · April 2026 · CAVU Aerospace UK Ltd · Edge-64 Block Diagrams
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