CAVU SpaceWire IP and Linux Drivers
- September 26, 2026
- CAVU Aerospace UK
SpaceWire is a lightweight, high-reliability serial interconnect designed for embedded and spacecraft data handling. Each direction uses independent data and strobe signaling, with the clock encoded in the transitions of those signals. The link is therefore full duplex: transmit and receive paths operate independently and may run at different data rates. Our receiver architecture uses oversampling to recover and decode incoming SpaceWire characters reliably.
CAVU’s SpaceWire IP and software stack support standard packet-based workflows, including CCSDS over SpaceWire and Remote Memory Access Protocol (RMAP), as well as custom packet formats. The same interface can be used to send and receive application packets, access RMAP memory targets, or expose the on-board computer as an RMAP-accessible memory resource.
The design is built for practical integration with Linux. Multi-descriptor DMA and in-flight packet buffering decouple the real-time SpaceWire link from operating-system interrupt latency, while descriptor-exhaustion handling makes buffer availability explicit. Packets that exceed the available internal FPGA SRAM can be transferred as smaller DMA segments and reassembled by the host application, avoiding an artificial limit on application packet size.
Multiple SpaceWire ports can be connected concurrently, allowing one on-board computer to collect sensor data, control spacecraft subsystems, and communicate with several independent nodes. Our camera module demonstrates this capability by transferring 5 MP image frames at 3.75 frames per second over a 200 Mbit/s SpaceWire link.
The IP also supports link-fault and protocol testing. Software can deliberately terminate a packet or transmit an error end-of-packet (EEP) marker, enabling applications to validate error handling and recovery behaviour before deployment.
A deterministic link for embedded data movement
SpaceWire provides a direct, point-to-point transport between embedded devices. Its separate transmit and receive paths allow an instrument, sensor, controller, or on-board computer to send and receive independently, without one transfer blocking the other. The encoded clock removes the need for a separate clock signal on the link, reducing interconnect complexity while preserving a synchronous character stream at the receiver.
For high-rate acquisition systems, this makes SpaceWire a strong fit for moving data from sensors into FPGA processing, on-board memory, or a Linux application. The link layer manages character encoding and flow control, allowing the application to focus on packet contents rather than low-level serial timing. Oversampling in the receive path provides the timing margin needed to recover the encoded character stream reliably.
Protocol flexibility without a proprietary data format
The CAVU interface does not constrain users to one packet format. CCSDS over SpaceWire can carry standard space-mission telemetry and command data, while RMAP provides controlled remote-memory access across the network. Applications that require their own binary protocol can send and receive custom packets through the same driver interface.
This flexibility supports several common deployment models:
– Sensor acquisition: receive high-rate instrument or camera data as application packets.
– On-board control: send commands and receive status from distributed spacecraft subsystems.
– RMAP initiator: read from or write to a remote RMAP target.
– RMAP target: expose local memory for access by another SpaceWire node.
– Gateway operation: forward packet data from SpaceWire to a Linux or Ethernet-connected application.
Linux-ready packet handling
Real-time serial links and general-purpose operating systems operate on different timescales. The FPGA continues to receive SpaceWire traffic while Linux schedules drivers, processes interrupts, and services applications. Multi-descriptor DMA and in-flight packet queues bridge this difference by allowing multiple packets to be transferred without requiring the processor to service every character or every packet immediately.
The software-visible descriptor model also makes receive-buffer ownership explicit. When buffers are available, the DMA engine can continue accepting packets; when descriptors are exhausted, the driver can report and manage that condition rather than silently discarding data. Large application packets can be divided into manageable DMA segments, transferred through the available memory resources, and reconstructed by the application.
Built for multi-node systems and verification
Multiple independent SpaceWire ports allow one platform to act as a concentrator for sensors, payloads, and subsystem controllers. The design can therefore scale from a simple point-to-point connection to a multi-node data-handling system without changing the fundamental software interface. The 5 MP camera demonstration, operating at 3.75 frames per second over a 200 Mbit/s link, is one example of sustained payload transport through this architecture.
Verification is part of the interface design, not an afterthought. Support for deliberate packet termination and EEP generation allows software teams to exercise error paths, confirm packet-boundary handling, and evaluate recovery behaviour under controlled fault conditions. This helps validate both the FPGA implementation and the Linux application before the system is deployed.
